Ashwani Kumar Gupta

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stalling predicted prefetch to memory location identified as uncach...
- Patent number 6,035,393
- Issue date Mar 7, 2000
- Intel Corporation
- Andrew F. Glew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,944,817
- Issue date Aug 31, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a branch target buffer in CIS...
- Patent number 5,903,751
- Issue date May 11, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system employing streaming buffer for instruction preetching
- Patent number 5,870,599
- Issue date Feb 9, 1999
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual instruction buffers with a bypass bus and rotator for a decode...
- Patent number 5,845,100
- Issue date Dec 1, 1998
- Intel Corporation
- Ashwani Kumar Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction fetch on demand for uncacheable memory which avoids mem...
- Patent number 5,819,079
- Issue date Oct 6, 1998
- Intel Corporation
- Andrew F. Glew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual prediction branch system having two step of branch recovery pr...
- Patent number 5,812,839
- Issue date Sep 22, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for predicting and handling resolving return f...
- Patent number 5,768,576
- Issue date Jun 16, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction length decoder for generating output length indicia to...
- Patent number 5,758,116
- Issue date May 26, 1998
- Intel Corporation
- Chan W. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for maintaining multilevel cache hierarchy coherency in a...
- Patent number 5,715,428
- Issue date Feb 3, 1998
- Intel Corporation
- Wen-Hann Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,706,492
- Issue date Jan 6, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction breakpoint detection apparatus for use in an out-of-ord...
- Patent number 5,694,589
- Issue date Dec 2, 1997
- Intel Corporation
- Andrew F. Glew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for maintaining a macro instruction for refetc...
- Patent number 5,687,338
- Issue date Nov 11, 1997
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for handling instructions from a branch prior to instruction...
- Patent number 5,608,885
- Issue date Mar 4, 1997
- Intel Corporation
- Ashwani K. Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for resolving return from subroutine instructi...
- Patent number 5,604,877
- Issue date Feb 18, 1997
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,574,871
- Issue date Nov 12, 1996
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING

Ashwani Kumar Gupta

Person

Patents Grantslast 30 patents

Stalling predicted prefetch to memory location identified as uncach...

Method and apparatus for implementing a set-associative branch targ...

Method and apparatus for implementing a branch target buffer in CIS...

Computer system employing streaming buffer for instruction preetching

Dual instruction buffers with a bypass bus and rotator for a decode...

Instruction fetch on demand for uncacheable memory which avoids mem...

Dual prediction branch system having two step of branch recovery pr...

Method and apparatus for predicting and handling resolving return f...

Instruction length decoder for generating output length indicia to...

Apparatus for maintaining multilevel cache hierarchy coherency in a...

Method and apparatus for implementing a set-associative branch targ...

Instruction breakpoint detection apparatus for use in an out-of-ord...

Method and apparatus for maintaining a macro instruction for refetc...

Method for handling instructions from a branch prior to instruction...

Method and apparatus for resolving return from subroutine instructi...

Method and apparatus for implementing a set-associative branch targ...