Aykut Dengi

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Tempe, AZ, US

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Patents Grantslast 30 patents

Information Patent Grant
Non-volatile logic device for energy-efficient logic state restoration
- Patent number 10,795,809
- Issue date Oct 6, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Jinghua Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock skewing strategy to reduce dynamic power and eliminate hold-t...
- Patent number 10,551,869
- Issue date Feb 4, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of obfuscating digital logic circuits using threshold voltage
- Patent number 9,876,503
- Issue date Jan 23, 2018
- Arixona Board of Regents on Behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for adding features to a design layout and process for desig...
- Patent number 6,593,226
- Issue date Jul 15, 2003
- Motorola, Inc.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a well under isolation and structure thereof
- Patent number 6,500,723
- Issue date Dec 31, 2002
- Motorola, Inc.
- Michael G. Khazhinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and a process for designing a mask
- Patent number 6,396,158
- Issue date May 28, 2002
- Motorola Inc.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NON-VOLATILE LOGIC DEVICE FOR ENERGY-EFFICIENT LOGIC STATE RESTORATION
- Publication number 20190213119
- Publication date Jul 11, 2019
- Arizona Board of Regents on behalf of Arizona State University
- Jinghua Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK SKEWING STRATEGY TO REDUCE DYNAMIC POWER AND ELIMINATE HOLD-T...
- Publication number 20170248989
- Publication date Aug 31, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE
- Publication number 20170187382
- Publication date Jun 29, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for adding features to a design layout and process for desig...
- Publication number 20020050655
- Publication date May 2, 2002
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS