Balasubramanian's Pranatharthiharan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Minimizing shorting between FinFET epitaxial regions
- Patent number 12,237,328
- Issue date Feb 25, 2025
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures including middle-of-line (MOL) capacitance...
- Patent number 12,237,368
- Issue date Feb 25, 2025
- Adeia Semiconductor Solutions LLC
- Injo Ok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with different channel widths
- Patent number 12,230,544
- Issue date Feb 18, 2025
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked nanosheet gate-all-around device structures
- Patent number 12,166,042
- Issue date Dec 10, 2024
- International Business Machines Corporation
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside electrical contacts to buried power rails
- Patent number 12,136,655
- Issue date Nov 5, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate thinning for a backside power distribution network
- Patent number 12,106,969
- Issue date Oct 1, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with early buried power rail (BPR) and backsid...
- Patent number 12,057,371
- Issue date Aug 6, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside metal-insulator-metal (MIM) capacitors extending through b...
- Patent number 12,002,758
- Issue date Jun 4, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having alternating selective metal and diel...
- Patent number 11,942,426
- Issue date Mar 26, 2024
- International Business Machines Corporation
- Son Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside power rail integration
- Patent number 11,915,966
- Issue date Feb 27, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite interconnect formation using graphene
- Patent number 11,908,734
- Issue date Feb 20, 2024
- International Business Machines Corporation
- Takeshi Nogami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around monolithic stacked field effect transistors having...
- Patent number 11,894,436
- Issue date Feb 6, 2024
- International Business Machines Corporation
- Julien Frougier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing shorting between FinFET epitaxial regions
- Patent number 11,664,375
- Issue date May 30, 2023
- TESSERA LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with different channel widths
- Patent number 11,538,720
- Issue date Dec 27, 2022
- TESSERA LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures including middle-of-line (MOL) capacitance...
- Patent number 11,522,045
- Issue date Dec 6, 2022
- TESSERA LLC
- Injo Ok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of performing fin cut etch processes for FinFET semiconduct...
- Patent number 11,469,146
- Issue date Oct 11, 2022
- GLOBALFOUNDRIES U.S. INC.
- Lei L. Zhuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanosheet transistors with sharp junctions
- Patent number 11,430,651
- Issue date Aug 30, 2022
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical field effect transistor with bottom source-drain region
- Patent number 11,355,633
- Issue date Jun 7, 2022
- International Business Machines Corporation
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin cut to prevent replacement gate collapse on STI
- Patent number 11,315,922
- Issue date Apr 26, 2022
- International Business Machines Corporation
- Andrew M. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnects including dual-metal vias
- Patent number 11,302,637
- Issue date Apr 12, 2022
- International Business Machines Corporation
- Balasubramanian S. Pranatharthi Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Approach to bottom dielectric isolation for vertical transport fin...
- Patent number 11,302,797
- Issue date Apr 12, 2022
- International Business Machines Corporation
- Zhenxing Bi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phase change memory using multiple phase change layers and multiple...
- Patent number 11,271,151
- Issue date Mar 8, 2022
- International Business Machines Corporation
- Injo Ok
- G11 - INFORMATION STORAGE
Information Patent Grant
Subtractive RIE interconnect
- Patent number 11,189,528
- Issue date Nov 30, 2021
- International Business Machines Corporation
- John Christopher Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective deposition with SAM for fully aligned via
- Patent number 11,171,054
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Son Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate contact compatible cross couple contact formation
- Patent number 11,164,782
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned isolation for nanosheet transistor
- Patent number 11,152,464
- Issue date Oct 19, 2021
- International Business Machines Corporation
- Balasubramanian S. Pranatharthi Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Late gate cut with optimized contact trench size
- Patent number 11,133,217
- Issue date Sep 28, 2021
- International Business Machines Corporation
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact-first field-effect transistors
- Patent number 11,101,367
- Issue date Aug 24, 2021
- International Business Machines Corporation
- Terence B. Hook
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Confined phase change memory with double air gap
- Patent number 11,063,216
- Issue date Jul 13, 2021
- International Business Machines Corporation
- Injo Ok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure of improving contact resistance for passive an...
- Patent number 11,038,055
- Issue date Jun 15, 2021
- International Business Machines Corporation
- Injo Ok
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ISOLATION MODULE FOR BACKSIDE POWER DELIVERY
- Publication number 20250040170
- Publication date Jan 30, 2025
- Applied Materials, Inc.
- Veeraraghavan S. BASKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL GROWTH OF STRAINED Si/SiGe SUPERLATTICE
- Publication number 20250037997
- Publication date Jan 30, 2025
- Applied Materials, Inc.
- Ruiying HAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE CONTACT FOR 3D MEMORY WITH CMOS BONDED ARRAY
- Publication number 20250022935
- Publication date Jan 16, 2025
- Applied Materials, Inc.
- Chang Seok Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT CAPPING WITH INTEGRATED PROCESS STEPS
- Publication number 20250006474
- Publication date Jan 2, 2025
- Applied Materials, Inc.
- Naomi YOSHIDA
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
REDUCED STRAIN AND STOP LAYER FOR Si/SiGe EPI STACKS
- Publication number 20240429048
- Publication date Dec 26, 2024
- Applied Materials, Inc.
- Ruiying HAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND FABRICATION METHOD OF PERIPHERAL TRANSISTOR WITH EPI-...
- Publication number 20240407170
- Publication date Dec 5, 2024
- Applied Materials, Inc.
- Chang Seok Kang
Information Patent Application
Three-Dimensional Vertical Interconnect Architecture and Methods Fo...
- Publication number 20240387458
- Publication date Nov 21, 2024
- Applied Materials, Inc.
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON CHANNEL FOR BONDED 3D NAND DEVICES
- Publication number 20240363345
- Publication date Oct 31, 2024
- Applied Materials, Inc.
- Chang Seok KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING...
- Publication number 20240365551
- Publication date Oct 31, 2024
- Applied Materials, Inc.
- Chang Seok Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE...
- Publication number 20240347602
- Publication date Oct 17, 2024
- Applied Materials, Inc.
- Fredrick FISHBURN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT
- Publication number 20240341090
- Publication date Oct 10, 2024
- Applied Materials, Inc.
- Sony VARGHESE
Information Patent Application
METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE
- Publication number 20240332388
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Byeong Chan Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPLACEMENT SOURCE/DRAIN CONTACT METHOD IN COMPLEMENTARY FIELD EFFE...
- Publication number 20240332297
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Ashish PAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES AND METHODS OF FORMING THE SAME
- Publication number 20240334683
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Tong Liu
Information Patent Application
Methods For Forming Gate Structures
- Publication number 20240304671
- Publication date Sep 12, 2024
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VOID-FREE STRESS INCORPORATION IN SEMICONDUCTOR DEVICES
- Publication number 20240290883
- Publication date Aug 29, 2024
- Applied Materials, Inc.
- Sai Hooi Yeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS INCORPORATION IN SEMICONDUCTOR DEVICES
- Publication number 20240290884
- Publication date Aug 29, 2024
- Applied Materials, Inc.
- El Mehdi Bazizi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED MOBILITY IN SEMICONDUCTOR DEVICES
- Publication number 20240290885
- Publication date Aug 29, 2024
- Applied Materials, Inc.
- Sai Hooi Yeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INNER SPACER LINER FOR GATE-ALL-AROUND DEVICE
- Publication number 20240234544
- Publication date Jul 11, 2024
- Applied Materials, Inc.
- Sai Hooi Yeong
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
INNER SPACER LINER FOR GATE-ALL-AROUND DEVICE
- Publication number 20240234531
- Publication date Jul 11, 2024
- Applied Materials, Inc.
- Sai Hooi Yeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL UNIFORMITY HORIZONTAL GATE ALL AROUND DEVICE
- Publication number 20240136229
- Publication date Apr 25, 2024
- Applied Materials, Inc.
- Jody FRONHEISER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIAL
- Publication number 20240120193
- Publication date Apr 11, 2024
- Applied Materials, Inc.
- Shankar Venkataraman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION
- Publication number 20240105505
- Publication date Mar 28, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION
- Publication number 20240105509
- Publication date Mar 28, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL LAYER FOR FORMING MERGED HIGH ASPECT RATIO CONTACTS IN...
- Publication number 20240090213
- Publication date Mar 14, 2024
- Applied Materials, Inc.
- Jialiang WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS
- Publication number 20240055426
- Publication date Feb 15, 2024
- TESSERA LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESSING METHODS AND CLUSTER TOOLS FOR FORMING SEMICONDUCTOR DEVICES
- Publication number 20240038553
- Publication date Feb 1, 2024
- Applied Materials, Inc.
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGY
- Publication number 20240014214
- Publication date Jan 11, 2024
- Applied Materials, Inc.
- Sai Hooi Yeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES
- Publication number 20240014076
- Publication date Jan 11, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT FORMATION PROCESS FOR CMOS DEVICES
- Publication number 20230377997
- Publication date Nov 23, 2023
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS

Balasubramanian's Pranatharthiharan

Person

Patents Grantslast 30 patents

Minimizing shorting between FinFET epitaxial regions

Semiconductor structures including middle-of-line (MOL) capacitance...

Stacked transistors with different channel widths

Stacked nanosheet gate-all-around device structures

Backside electrical contacts to buried power rails

Substrate thinning for a backside power distribution network

Semiconductor device with early buried power rail (BPR) and backsid...

Backside metal-insulator-metal (MIM) capacitors extending through b...

Semiconductor structure having alternating selective metal and diel...

Backside power rail integration

Composite interconnect formation using graphene

Gate-all-around monolithic stacked field effect transistors having...

Minimizing shorting between FinFET epitaxial regions

Stacked transistors with different channel widths

Semiconductor structures including middle-of-line (MOL) capacitance...

Methods of performing fin cut etch processes for FinFET semiconduct...

Nanosheet transistors with sharp junctions

Vertical field effect transistor with bottom source-drain region

Fin cut to prevent replacement gate collapse on STI

Interconnects including dual-metal vias

Approach to bottom dielectric isolation for vertical transport fin...

Phase change memory using multiple phase change layers and multiple...

Subtractive RIE interconnect

Selective deposition with SAM for fully aligned via

Self-aligned gate contact compatible cross couple contact formation

Self-aligned isolation for nanosheet transistor

Late gate cut with optimized contact trench size

Contact-first field-effect transistors

Confined phase change memory with double air gap

Method and structure of improving contact resistance for passive an...

Patents Applicationslast 30 patents

ISOLATION MODULE FOR BACKSIDE POWER DELIVERY

EPITAXIAL GROWTH OF STRAINED Si/SiGe SUPERLATTICE

SOURCE CONTACT FOR 3D MEMORY WITH CMOS BONDED ARRAY

INTERCONNECT CAPPING WITH INTEGRATED PROCESS STEPS

REDUCED STRAIN AND STOP LAYER FOR Si/SiGe EPI STACKS

STRUCTURE AND FABRICATION METHOD OF PERIPHERAL TRANSISTOR WITH EPI-...

Three-Dimensional Vertical Interconnect Architecture and Methods Fo...

SILICON CHANNEL FOR BONDED 3D NAND DEVICES

3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING...

REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE...

DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT

METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE

REPLACEMENT SOURCE/DRAIN CONTACT METHOD IN COMPLEMENTARY FIELD EFFE...

MEMORY DEVICES AND METHODS OF FORMING THE SAME

Methods For Forming Gate Structures

VOID-FREE STRESS INCORPORATION IN SEMICONDUCTOR DEVICES

STRESS INCORPORATION IN SEMICONDUCTOR DEVICES

ENHANCED MOBILITY IN SEMICONDUCTOR DEVICES

INNER SPACER LINER FOR GATE-ALL-AROUND DEVICE

INNER SPACER LINER FOR GATE-ALL-AROUND DEVICE

CHANNEL UNIFORMITY HORIZONTAL GATE ALL AROUND DEVICE

CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIAL

MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION

MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION

SACRIFICIAL LAYER FOR FORMING MERGED HIGH ASPECT RATIO CONTACTS IN...

MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS

PROCESSING METHODS AND CLUSTER TOOLS FOR FORMING SEMICONDUCTOR DEVICES

INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGY

SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES

CONTACT FORMATION PROCESS FOR CMOS DEVICES