Balasubramanian's Pranatharthiharan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-cut and separation techniques for enabling independent gate co...
- Patent number 12,336,294
- Issue date Jun 17, 2025
- International Business Machines Corporation
- Ruilong Xie
Information Patent Grant
Phase change memory using multiple phase change layers and multiple...
- Patent number 12,310,264
- Issue date May 20, 2025
- International Business Machines Corporation
- Injo Ok
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked FETS with non-shared work function metals
- Patent number 12,278,237
- Issue date Apr 15, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside power rails and power distribution network for density sca...
- Patent number 12,268,031
- Issue date Apr 1, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing shorting between FinFET epitaxial regions
- Patent number 12,237,328
- Issue date Feb 25, 2025
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures including middle-of-line (MOL) capacitance...
- Patent number 12,237,368
- Issue date Feb 25, 2025
- Adeia Semiconductor Solutions LLC
- Injo Ok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with different channel widths
- Patent number 12,230,544
- Issue date Feb 18, 2025
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked nanosheet gate-all-around device structures
- Patent number 12,166,042
- Issue date Dec 10, 2024
- International Business Machines Corporation
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside electrical contacts to buried power rails
- Patent number 12,136,655
- Issue date Nov 5, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate thinning for a backside power distribution network
- Patent number 12,106,969
- Issue date Oct 1, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with early buried power rail (BPR) and backsid...
- Patent number 12,057,371
- Issue date Aug 6, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside metal-insulator-metal (MIM) capacitors extending through b...
- Patent number 12,002,758
- Issue date Jun 4, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having alternating selective metal and diel...
- Patent number 11,942,426
- Issue date Mar 26, 2024
- International Business Machines Corporation
- Son Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside power rail integration
- Patent number 11,915,966
- Issue date Feb 27, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite interconnect formation using graphene
- Patent number 11,908,734
- Issue date Feb 20, 2024
- International Business Machines Corporation
- Takeshi Nogami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around monolithic stacked field effect transistors having...
- Patent number 11,894,436
- Issue date Feb 6, 2024
- International Business Machines Corporation
- Julien Frougier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing shorting between FinFET epitaxial regions
- Patent number 11,664,375
- Issue date May 30, 2023
- TESSERA LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with different channel widths
- Patent number 11,538,720
- Issue date Dec 27, 2022
- TESSERA LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures including middle-of-line (MOL) capacitance...
- Patent number 11,522,045
- Issue date Dec 6, 2022
- TESSERA LLC
- Injo Ok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of performing fin cut etch processes for FinFET semiconduct...
- Patent number 11,469,146
- Issue date Oct 11, 2022
- GLOBALFOUNDRIES U.S. INC.
- Lei L. Zhuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanosheet transistors with sharp junctions
- Patent number 11,430,651
- Issue date Aug 30, 2022
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical field effect transistor with bottom source-drain region
- Patent number 11,355,633
- Issue date Jun 7, 2022
- International Business Machines Corporation
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin cut to prevent replacement gate collapse on STI
- Patent number 11,315,922
- Issue date Apr 26, 2022
- International Business Machines Corporation
- Andrew M. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnects including dual-metal vias
- Patent number 11,302,637
- Issue date Apr 12, 2022
- International Business Machines Corporation
- Balasubramanian S. Pranatharthi Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Approach to bottom dielectric isolation for vertical transport fin...
- Patent number 11,302,797
- Issue date Apr 12, 2022
- International Business Machines Corporation
- Zhenxing Bi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phase change memory using multiple phase change layers and multiple...
- Patent number 11,271,151
- Issue date Mar 8, 2022
- International Business Machines Corporation
- Injo Ok
- G11 - INFORMATION STORAGE
Information Patent Grant
Subtractive RIE interconnect
- Patent number 11,189,528
- Issue date Nov 30, 2021
- International Business Machines Corporation
- John Christopher Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective deposition with SAM for fully aligned via
- Patent number 11,171,054
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Son Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate contact compatible cross couple contact formation
- Patent number 11,164,782
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned isolation for nanosheet transistor
- Patent number 11,152,464
- Issue date Oct 19, 2021
- International Business Machines Corporation
- Balasubramanian S. Pranatharthi Haran
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND DEVICES FOR REDUCED FLOATING BODY EFFECT IN ADVANCED DRAM
- Publication number 20250227915
- Publication date Jul 10, 2025
- Applied Materials, Inc.
- Ashish PAL
Information Patent Application
SELF-ALIGNING BACKSIDE GATE CONNECTION
- Publication number 20250218870
- Publication date Jul 3, 2025
- Applied Materials, Inc.
- Ashish PAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS
- Publication number 20250212459
- Publication date Jun 26, 2025
- Applied Materials, Inc.
- Nicolas BREIL
Information Patent Application
METHODS OF FORMING MEMORY STRUCTURES USING SEAMLESS GAPFILL
- Publication number 20250185230
- Publication date Jun 5, 2025
- Applied Materials, Inc.
- Fredrick Fishburn
Information Patent Application
SELECTIVE SILICON NITRIDE WITH TREATMENT FOR CONTACT FORMATION IN L...
- Publication number 20250183036
- Publication date Jun 5, 2025
- Applied Materials, Inc.
- Naomi Yoshida
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS
- Publication number 20250169157
- Publication date May 22, 2025
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS
- Publication number 20250169171
- Publication date May 22, 2025
- Adeia Semiconductor Solutions LLC
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
N-CHANNEL COUPLED WITH P-CHANNEL AND METHODS OF MANUFACTURE
- Publication number 20250142957
- Publication date May 1, 2025
- Applied Materials, Inc.
- Sai Hooi Yeong
Information Patent Application
ENGINEERING EPI STACKS FOR EXTREME WAFER THINNING
- Publication number 20250132163
- Publication date Apr 24, 2025
- Applied Materials, Inc.
- Raghuveer Satya MAKALA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL FILM DEFECT DETERMINATION
- Publication number 20250117754
- Publication date Apr 10, 2025
- Applied Materials, Inc.
- Ruiying Hao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM
- Publication number 20250120065
- Publication date Apr 10, 2025
- Applied Materials, Inc.
- Zhijun CHEN
Information Patent Application
SELF-ALIGNED BIT LINE FOR 4F2 DRAM
- Publication number 20250120069
- Publication date Apr 10, 2025
- Applied Materials, Inc.
- Zhijun CHEN
Information Patent Application
PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONT...
- Publication number 20250120068
- Publication date Apr 10, 2025
- Applied Materials, Inc.
- Zhijun CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR AIRGAP SPACER AND FABRICATION METHODS
- Publication number 20250113577
- Publication date Apr 3, 2025
- Applied Materials, Inc.
- Veeraraghavan S. Basker
Information Patent Application
CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS TO REDUCE THIC...
- Publication number 20250112054
- Publication date Apr 3, 2025
- Applied Materials, Inc.
- Yuriy Shusterman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D Memory Mold Film Stack
- Publication number 20250113522
- Publication date Apr 3, 2025
- Applied Materials, Inc.
- Ruiying HAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL WORK FUNCTION WORD LINE FOR 4F2
- Publication number 20250107068
- Publication date Mar 27, 2025
- Applied Materials, Inc.
- Tong LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ALL AROUND 4F2 DRAM
- Publication number 20250081432
- Publication date Mar 6, 2025
- Applied Materials, Inc.
- Zhijun CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION MODULE FOR BACKSIDE POWER DELIVERY
- Publication number 20250040170
- Publication date Jan 30, 2025
- Applied Materials, Inc.
- Veeraraghavan S. BASKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL GROWTH OF STRAINED Si/SiGe SUPERLATTICE
- Publication number 20250037997
- Publication date Jan 30, 2025
- Applied Materials, Inc.
- Ruiying HAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE CONTACT FOR 3D MEMORY WITH CMOS BONDED ARRAY
- Publication number 20250022935
- Publication date Jan 16, 2025
- Applied Materials, Inc.
- Chang Seok Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT CAPPING WITH INTEGRATED PROCESS STEPS
- Publication number 20250006474
- Publication date Jan 2, 2025
- Applied Materials, Inc.
- Naomi YOSHIDA
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
REDUCED STRAIN AND STOP LAYER FOR Si/SiGe EPI STACKS
- Publication number 20240429048
- Publication date Dec 26, 2024
- Applied Materials, Inc.
- Ruiying HAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND FABRICATION METHOD OF PERIPHERAL TRANSISTOR WITH EPI-...
- Publication number 20240407170
- Publication date Dec 5, 2024
- Applied Materials, Inc.
- Chang Seok Kang
Information Patent Application
Three-Dimensional Vertical Interconnect Architecture and Methods Fo...
- Publication number 20240387458
- Publication date Nov 21, 2024
- Applied Materials, Inc.
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON CHANNEL FOR BONDED 3D NAND DEVICES
- Publication number 20240363345
- Publication date Oct 31, 2024
- Applied Materials, Inc.
- Chang Seok KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING...
- Publication number 20240365551
- Publication date Oct 31, 2024
- Applied Materials, Inc.
- Chang Seok Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE...
- Publication number 20240347602
- Publication date Oct 17, 2024
- Applied Materials, Inc.
- Fredrick FISHBURN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT
- Publication number 20240341090
- Publication date Oct 10, 2024
- Applied Materials, Inc.
- Sony VARGHESE
Information Patent Application
METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE
- Publication number 20240332388
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Byeong Chan Lee
- H01 - BASIC ELECTRIC ELEMENTS

Balasubramanian's Pranatharthiharan

Person

Patents Grantslast 30 patents

Gate-cut and separation techniques for enabling independent gate co...

Phase change memory using multiple phase change layers and multiple...

Stacked FETS with non-shared work function metals

Backside power rails and power distribution network for density sca...

Minimizing shorting between FinFET epitaxial regions

Semiconductor structures including middle-of-line (MOL) capacitance...

Stacked transistors with different channel widths

Stacked nanosheet gate-all-around device structures

Backside electrical contacts to buried power rails

Substrate thinning for a backside power distribution network

Semiconductor device with early buried power rail (BPR) and backsid...

Backside metal-insulator-metal (MIM) capacitors extending through b...

Semiconductor structure having alternating selective metal and diel...

Backside power rail integration

Composite interconnect formation using graphene

Gate-all-around monolithic stacked field effect transistors having...

Minimizing shorting between FinFET epitaxial regions

Stacked transistors with different channel widths

Semiconductor structures including middle-of-line (MOL) capacitance...

Methods of performing fin cut etch processes for FinFET semiconduct...

Nanosheet transistors with sharp junctions

Vertical field effect transistor with bottom source-drain region

Fin cut to prevent replacement gate collapse on STI

Interconnects including dual-metal vias

Approach to bottom dielectric isolation for vertical transport fin...

Phase change memory using multiple phase change layers and multiple...

Subtractive RIE interconnect

Selective deposition with SAM for fully aligned via

Self-aligned gate contact compatible cross couple contact formation

Self-aligned isolation for nanosheet transistor

Patents Applicationslast 30 patents

METHODS AND DEVICES FOR REDUCED FLOATING BODY EFFECT IN ADVANCED DRAM

SELF-ALIGNING BACKSIDE GATE CONNECTION

METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS

METHODS OF FORMING MEMORY STRUCTURES USING SEAMLESS GAPFILL

SELECTIVE SILICON NITRIDE WITH TREATMENT FOR CONTACT FORMATION IN L...

STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS

MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS

N-CHANNEL COUPLED WITH P-CHANNEL AND METHODS OF MANUFACTURE

ENGINEERING EPI STACKS FOR EXTREME WAFER THINNING

EPITAXIAL FILM DEFECT DETERMINATION

SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM

SELF-ALIGNED BIT LINE FOR 4F2 DRAM

PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONT...

SEMICONDUCTOR AIRGAP SPACER AND FABRICATION METHODS

CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS TO REDUCE THIC...

3D Memory Mold Film Stack

DUAL WORK FUNCTION WORD LINE FOR 4F2

GATE ALL AROUND 4F2 DRAM

ISOLATION MODULE FOR BACKSIDE POWER DELIVERY

EPITAXIAL GROWTH OF STRAINED Si/SiGe SUPERLATTICE

SOURCE CONTACT FOR 3D MEMORY WITH CMOS BONDED ARRAY

INTERCONNECT CAPPING WITH INTEGRATED PROCESS STEPS

REDUCED STRAIN AND STOP LAYER FOR Si/SiGe EPI STACKS

STRUCTURE AND FABRICATION METHOD OF PERIPHERAL TRANSISTOR WITH EPI-...

Three-Dimensional Vertical Interconnect Architecture and Methods Fo...

SILICON CHANNEL FOR BONDED 3D NAND DEVICES

3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING...

REDUCED STRAIN HETEROEPITAXY ASSEMBLY FOR THREE-DIMENSIONAL DEVICE...

DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT

METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE