Patent Application
20240387458
Embodiments of the present principles generally relate to processing of semiconductor substrates.
Advances in artificial intelligence have put ever increasing pressure on logic and memory circuits to keep up with the computational requirements. As chip processing speeds increase, the amount of time required to store and retrieve information from memory becomes a bottleneck in machine learning systems. The inventors have observed that the parallel arrangement of logic and memory devices has a profound impact on the storage and retrieval time for memory data.
Accordingly, the inventors have provided an architecture and methods of forming that substantially decrease the storage and retrieval time for data, increasing machine learning system processing speeds.
Architectures and methods for forming that substantially decrease memory storage and retrieval times are provided herein.
In some embodiments, a method for forming a multiple die stack may comprise forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, and hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies, wherein the interposer wafer provides structural support of the first bonded wafer during subsequent processing.
In some embodiments, the method may further include flipping the first bonded wafer to expose the first circuit support layer of the first circuit wafer and performing a first chemical mechanical polishing (CMP) process or a first etching process on the first circuit wafer to remove the first circuit support layer to expose a plurality of power vias in the power and circuit layer of the first circuit wafer, forming a power delivery network (PDN) layer directly on the first circuit wafer, the PDN layer having a top surface with internal power contacts interfacing with the power and circuit layer of the first circuit wafer and a bottom surface with external power contacts, wherein the internal power contacts of the PDN layer make contact with the power and circuit layer to electrically connect the internal power contacts of the PDN layer to the plurality of power vias in the power and circuit layer of the first circuit wafer to form a second bonded wafer from the first bonded wafer, and/or flipping the second bonded wafer to expose the top surface of the interposer wafer and performing a second CMP process or a second etching process on the interposer support layer to expose contact points of the power via and signal via layer of the interposer wafer.
In some embodiments, the method may further include reducing the interposer wafer to a total thickness of approximately 100 microns to approximately 200 microns when using vias with a critical dimension of approximately 5 microns to approximately 20 microns, reducing the interposer wafer to a total thickness of approximately 5 microns to approximately 10 microns when using vias with a critical dimension of approximately 2 microns to approximately 4 microns, forming a second circuit wafer with multiple second circuit dies, each second circuit die having a bottom surface with at least one signal contact and at least one power contact for electrically interconnecting with the multiple interposer dies of the interposer wafer, hybrid bonding the bottom surface of the second circuit wafer to the top surface of the interposer wafer to form a third bonded wafer from the second bonded wafer to electrically connect the at least one signal contact and the at least one power contact to the multiple interposer dies of the interposer wafer and dicing the third bonded wafer to form electrically connected vertical die stacks, each vertical die stack has one portion of the PDN layer, one of the first circuit die, one of the interposer die, and one of the second circuit die to form a complete vertical die stack with backside power capability, and/or forming a heatsink in contact with the second circuit die to remove heat from underlying circuits.
In some embodiments, the method may further include forming at least one heat sink for an external power contact of the PDN layer in a substrate with contacts for electrically connecting with the PDN layer and electrically connecting the PDN layer to the substrate, dicing the second bonded wafer after performing the second CMP process or the second etching process to form partial vertical die stacks that are electrically connected from the second bonded wafer, dicing the second circuit wafer to form second circuit dies, and hybrid bonding one of the second circuit dies to one of the partial vertical die stacks to form a complete vertical die stack with backside power capability, forming a heatsink in contact with the second circuit die to remove heat from underlying circuits, and/or forming at least one heat sink for an external power contact of the PDN layer in a substrate with contacts for electrically connecting with the PDN layer and electrically connecting the PDN layer to the substrate.
In some embodiments, a method for forming a multiple die stack may include forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies where the interposer wafer provides structural support of the first bonded wafer during subsequent processing, flipping the first bonded wafer to expose the first circuit support layer of the first circuit wafer, performing a first chemical mechanical polishing (CMP) process or a first etching process on the first circuit wafer to remove the first circuit support layer to expose a plurality of power vias in the power and circuit layer of the first circuit wafer, forming a power delivery network (PDN) layer directly on the first circuit wafer, the PDN layer having a top surface with internal power contacts interfacing with the power and circuit layer of the first circuit wafer and a bottom surface with external power contacts where the internal power contacts of the PDN layer make contact with the power and circuit layer to electrically connect the internal power contacts of the PDN layer to the plurality of power vias in the power and circuit layer of the first circuit wafer to form a second bonded wafer from the first bonded wafer, flipping the second bonded wafer to expose the top surface of the interposer wafer, performing a second CMP process or a second etching process on the interposer support layer to expose contact points of the power via and signal via layer of the interposer wafer such that a thickness of the interposer wafer is approximately 100 microns to approximately 200 microns, forming a second circuit wafer with multiple second circuit dies, each second circuit die having a bottom surface with at least one signal contact and at least one power contact for electrically interconnecting with the multiple interposer dies of the interposer wafer, hybrid bonding the bottom surface of the second circuit wafer to the top surface of the interposer wafer to form a third bonded wafer from the second bonded wafer to electrically connect the at least one signal contact and the at least one power contact to the multiple interposer dies of the interposer wafer and dicing the third bonded wafer to form electrically connected vertical die stacks, each vertical die stack has one portion of the PDN layer, one of the first circuit die, one of the interposer die, and one of the second circuit die to form a complete vertical die stack with backside power capability.
In some embodiments, the method may further include forming a heatsink in contact with the second circuit die to remove heat from underlying circuits and/or forming at least one heat sink for an external power contact of the PDN layer in a substrate with contacts for electrically connecting with the PDN layer, and electrically connecting the PDN layer to the substrate.
In some embodiments, a die stack with a vertical architecture may comprise a power delivery network (PDN) layer with a first backside power path and a first circuit power path, a first circuit die with a first circuit, a second circuit power path electrically connected to the first circuit and the first circuit power path of the PDN layer, a second backside power path electrically connected to the first backside power path of the PDN layer, and a first signal path electrically connected to the first circuit, an interposer die with a third backside power path electrically connected to the second backside power path of the first circuit die and a second signal path electrically connected to the first signal path of the first circuit die, and a second circuit die with a power contact electrically connected to the third backside power path of the interposer die and a signal contact electrically connected to the second signal path of the interposer die.
In some embodiments, the die stack may further comprise an interposer die that further includes a signal altering element interposed in the second signal path that electrically alters signal characteristics of signals traveling on the second signal path prior to reaching the second circuit die, a first circuit die that includes a plurality of first circuits and a plurality of first signal paths and a plurality of second circuit power paths and wherein the PDN layer includes a plurality of first circuit power paths that are electrically connected to the plurality of second circuit power paths in the first circuit die, and/or a heatsink in thermal contact with a top surface of the second circuit die.
Other and further embodiments are disclosed below.
Embodiments of the present principles, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative embodiments of the principles depicted in the appended drawings. However, the appended drawings illustrate only typical embodiments of the principles and are thus not to be considered limiting of scope, for the principles may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Architectures and methods for forming the architectures provide a multiple chip vertical and local interconnect. The methods feature wafer level flows to create backside power rail connections and combine silicon (Si) interposers for creating multiple chip interconnects. By forming vertical connections, the architecture minimizes RC delay between logic and memory devices, providing an innovative design for artificial intelligence (AI)/machine learning (ML) and neuromorphic applications. RC delay improvements provided by the present architecture may have 50 to 100 times or more in reduction in RC delay over traditional parallel type architectures. The architecture of the present methods allows vertical interconnections between logic and memory built on separate chips (from separate wafers), reducing the interconnect distance from a few centimeters or more to a few microns or less. The narrow pitch of the vertical interconnects with local connections beneficially allows for increased connection density, allowing more iterations or calculations to be possible over traditional architectures.
Current connections of multiple laterally situated chips require a combination of through silicon via (TSV) and wire bonding, resulting in long lateral interconnects from chip to chip (e.g., a typical size of a chip=1-20 mm). Thus, resulting in a large RC delay as well as a limited number of possible connections. The present principles combine backside power rail chip connections plus a novel Si interposer that provides a high density of vertical connections and is also used as support during formation of the vertical chip stack. The present architecture allows for high density connections between logic and memory devices by using a Si interposer that provides short (less than 200 microns) direct vertical connections. The power connections are nano TSV sized connections between the logic and power delivery network (PDN) to the substrate and can be formed using back-end-of-line (BEOL) processes.
The PDN layer 106 is formed on a wafer that contains a first circuit die 104. The first circuit die 104 includes a power distribution and circuit layer 126 and a power distribution and signal layer 124. In some embodiments, the first circuit die 104 may be a logic circuit and the like or a processor circuit and the like. The power distribution and circuit layer 126 incudes one or more feedthrough power via 132 electrically connected to the feedthrough power connection 138 of the PDN layer 106, one or more first circuit power via 136 electrically connected to the local power connection 140, and one or more first circuit 134 electrically connected to the local power connection 140. In some embodiments, the first circuit power vias 136 are nano-sized connections between the first circuit 134 and the PDN layer 106. The power distribution and signal layer 124 includes one or more feedthrough power connection 128 electrically connected to the feedthrough power via 132 and one or more signal connection 130 electrically connected to the first circuit 134. The first circuit die 104 is bonded to the interposer die 102.
In some embodiments, the interposer die 102 is formed of a low-k dielectric material with copper interconnects and the like. The interposer die 102 includes a power and signal connection layer 114 that includes one or more feedthrough power connection 122 and one or more signal connection 120 with signal altering elements 164. The signal altering elements 164 may include, but are not limited to, resistive elements, inductive elements, and/or capacitive elements and the like that aid in adjusting signal characteristics of signals from the first circuit 134 being sent to dies above the first circuit die 104 (e.g., signals from the first circuit 134 traversing the interposer die 102 to the second circuit die 108, etc.). The signal connection 120 is electrically connected to the signal connection 130 of the first circuit die 104. The feedthrough power connection 122 is electrically connected to the feedthrough power connection 128 of the first circuit die 104.
The interposer die 102 also includes a power and signal via layer 112 that has a feedthrough power via 118 to supply power from the PDN layer 106 to an upper die such as, for example, the second circuit die 108. The feedthrough power via 118 is electrically connected to the feedthrough power connection 122. The power and signal via layer 112 also includes one or more signal vias 116 which are electrically connected to the signal connection 120 to supply signals to an upper die such as, for example, the second circuit die 108. In some embodiments, the signal vias 116 may have a CD of approximately 5 microns to approximately 20 microns to provide a high-density level of connections between the first circuit 134 and the second circuit 146. The second circuit die 108 is bonded to the interposer die 102. The second circuit die 108 includes a power contact 148 that is electrically connected to the feedthrough power via 118 of the interposer die 102. The feedthrough power connection 138, the feedthrough power via 132, the feedthrough power connection 128, the feedthrough power connection 122, and the feedthrough power via 118 act in concert to deliver power to the second circuit die 108 from the PDN layer 106 in a backside power delivery architecture.
The second circuit die 108 also includes one or more signal contact 150 that is electrically connected to the signal via 116 of the interposer die 102. In some embodiments, the second circuit die 108 is a memory device and the like or a processor or logic device and the like. The signal connection 130, the signal connection 120, and the signal via 116 act in concert to deliver and receive signals (and alter signal characteristics if necessary for compatibility) to and from the first circuit 134 and the second circuit 146 of the second circuit die 108. In some embodiments, the thickness 170 of the interposer die 102 may be from approximately 100 microns to approximately 300 microns. In some embodiments, the thickness 170 of the interposer die 102 may be approximately 50 microns or less. The thickness 172 of the power and signal connection layer of the first circuit die 104 may be from approximately 2 microns to approximately 3 microns. The total signal distance between the first circuit 134 and the second circuit 146 is substantially reduced over parallel-type circuit architectures where dies are bonded side-by-side and may require further wire bonding techniques for signal connections. The final interposer thickness may be based on density of through silicon vias and via depth. For example, with approximately 20 micron vias, the interposer thickness may be from approximately 100 microns to approximately 200 microns. With sub one micron vias to approximately 4 micron vias, the interposer thickness may be from approximately 5 microns to approximately 10 microns (with additional support on PDN layer).
The dramatic reduction in RC delay (due to the substantially shortened electrical distance between the first circuit 134 and the second circuit 146) for the signals enables exceptionally fast signal transfers. For example, if the first circuit 134 is a logic circuit and the second circuit 146 is a memory circuit, storing and retrieving of data is fast enough to allow further advances in machine learning/artificial intelligence devices that have a heavy load demand on memory during processing tasks. The increased density of connections between the memory and logic circuits also allows a dramatic increase in the number of logical calculations and the like. With higher speeds between the circuits and higher connection densities, thermal issues may arise in the vertical stack 160. In a view 200 of
In
References to
In block 304 and as shown in a view 500 of
In block 306 as depicted in a view 600 of
In block 310 as depicted in a view 800 of
In block 312 as depicted in a view 900 of
In block 314 as depicted in a view 1000 of
In the alternative after block 314, in block 320, the bonded wafer can be diced to singulate a stacked die 1302 with a PDN layer 106, a first circuit die 104, and an interposer die 102 as depicted in a view 1300A of
In addition, the above methods can be used to increase the number of dies in the vertical stack 160 as depicted in a view 1400 of
Signals provided to and from the first circuit 134 can also be extended to upper dies in the vertical stack 160. The first circuit die 104 can have more than one first circuit 134 but only one is depicted to keep the discussion brief. A signal connection 120 is provided through the interposer die 102 via signal altering elements 164 to the signal contact 150 of the second circuit die 108. If a third circuit die 1402 is added and functions, for example, as additional memory similar to the second circuit die 108, an optional first signal pathway 120A may be added in the interposer die 102 and the second circuit die 108 to provide a signal pathway to a signal contact 1422 of the third circuit die 1402 after the signal altering elements 164 of the interposer die 102. In some embodiments, the optional first signal pathway 120A may originate from within the second circuit die 108 (e.g., signal contact 150, etc.) and traverse the second circuit die 108 to the third circuit die 1402.
However, if the signals from the first circuit die 104 require different signal altering, the interposer die 102 may have optional signal altering elements 164B in an optional second signal pathway 120B from the first circuit 134 through the second circuit die 108 and the third circuit die 1402 to a signal contact 1424 of the fourth circuit die 1404. The example is not meant to be limiting and is depicts the flexibility of the architecture to continually add addition dies with minimal impacts to the underlying dies. The underlying dies will have an additional backside power pathway segment and, in some embodiments, an additional signal pathway or two depending on the number of dies added to the vertical stack 160. The interposer die 102 may also have additional signal altering elements and signal pathways. The additional signal pathway distance (RC delay) for each added circuit will be the thicknesses of the underlying circuits between the added circuit and the first circuit 134.
Embodiments in accordance with the present principles may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may also be implemented as instructions stored using one or more computer readable media, which may be read and executed by one or more processors. A computer readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform or a “virtual machine” running on one or more computing platforms). For example, a computer readable medium may include any suitable form of volatile or non-volatile memory. In some embodiments, the computer readable media may include a non-transitory computer readable medium.
While the foregoing is directed to embodiments of the present principles, other and further embodiments of the principles may be devised without departing from the basic scope thereof.
