Ban P. WONG

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Partially depopulated interconnection arrays for packaged semicondu...
- Patent number 9,820,389
- Issue date Nov 14, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Ban Pak Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ROM segmented bitline circuit
- Patent number 9,704,874
- Issue date Jul 11, 2017
- eASIC Corporation
- Ban P. Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Partially depopulated interconnection arrays for packaged semicondu...
- Patent number 9,345,137
- Issue date May 17, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Ban Pak Wong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package with input capacitance compensation
- Patent number 8,643,168
- Issue date Feb 4, 2014
- Lattice Semiconductor Corporation
- Ban P. Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Complementary pass gate logic implementation of 64-bit arithmetic l...
- Patent number 7,194,501
- Issue date Mar 20, 2007
- Sun Microsystems, Inc.
- Sanjay Dubey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for scan testing and clocking dynamic domino circuits in VLS...
- Patent number 7,000,164
- Issue date Feb 14, 2006
- Sun Microsystems, Inc.
- Joseph R. Siegel
- G01 - MEASURING TESTING
Information Patent Grant
Method to reduce leakage during a semi-conductor burn-in procedure
- Patent number 6,649,425
- Issue date Nov 18, 2003
- Sun Microsystems, Inc.
- Ban P. Wong
- G01 - MEASURING TESTING
Information Patent Grant
Controlled slew rate output buffer
- Patent number 5,519,338
- Issue date May 21, 1996
- MicroUnity Systems Engineering, Inc.
- John G. Campbell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BiCMOS memory cell with current access
- Patent number 5,432,736
- Issue date Jul 11, 1995
- MicroUnity Systems Engineering, Inc.
- Ban P. Wong
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Memory Circuits And Methods With Write Assist
- Publication number 20220108733
- Publication date Apr 7, 2022
- Intel Corporation
- Wayson Lowe
- G11 - INFORMATION STORAGE
Information Patent Application
Circuits And Methods For Routing Crossbars With Programmable Vias
- Publication number 20220014197
- Publication date Jan 13, 2022
- Intel Corporation
- Atul Maheshwari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuits And Methods For Programmable Memory
- Publication number 20210111721
- Publication date Apr 15, 2021
- Intel Corporation
- Ban Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Via-Configurable Memory
- Publication number 20200027828
- Publication date Jan 23, 2020
- Intel Corporation
- Wayson Lowe
- G11 - INFORMATION STORAGE
Information Patent Application
ROM SEGMENTED BITLINE CIRCUIT
- Publication number 20170170186
- Publication date Jun 15, 2017
- eASIC Corporation
- Ban P. WONG
- G11 - INFORMATION STORAGE
Information Patent Application
Partially Depopulated Interconnection Arrays for Packaged Semicondu...
- Publication number 20160242298
- Publication date Aug 18, 2016
- Lattice Semiconductor Corporation
- Ban Pak Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
META-STABILITY PREVENTION FOR OSCILLATORS
- Publication number 20160134264
- Publication date May 12, 2016
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A...
- Publication number 20160124899
- Publication date May 5, 2016
- eASIC Corporation
- Ronnie VASISHTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partially Depopulated Interconnection Arrays for Packaged Semicondu...
- Publication number 20150124419
- Publication date May 7, 2015
- Lattice Semiconductor Corporation
- Ban Pak Wong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Complementary pass gate logic implementation of 64-bit arithmetic l...
- Publication number 20040078417
- Publication date Apr 22, 2004
- SUN MICROSYSTEMS, INC.
- Sanjay Dubey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for scan testing and clocking dynamic domino circuits in VLS...
- Publication number 20030145264
- Publication date Jul 31, 2003
- SUN MICROSYSTEMS, INC.
- Joseph R. Siegel
- G01 - MEASURING TESTING
Information Patent Application
Method to reduce leakage during a semi-conductor burn-in procedure
- Publication number 20020146852
- Publication date Oct 10, 2002
- Ban P. Wong
- G01 - MEASURING TESTING

Ban P. WONG

Person

Patents Grantslast 30 patents

Partially depopulated interconnection arrays for packaged semicondu...

ROM segmented bitline circuit

Partially depopulated interconnection arrays for packaged semicondu...

Integrated circuit package with input capacitance compensation

Complementary pass gate logic implementation of 64-bit arithmetic l...

Method for scan testing and clocking dynamic domino circuits in VLS...

Method to reduce leakage during a semi-conductor burn-in procedure

Controlled slew rate output buffer

BiCMOS memory cell with current access

Patents Applicationslast 30 patents

Memory Circuits And Methods With Write Assist

Circuits And Methods For Routing Crossbars With Programmable Vias

Circuits And Methods For Programmable Memory

Via-Configurable Memory

ROM SEGMENTED BITLINE CIRCUIT

Partially Depopulated Interconnection Arrays for Packaged Semicondu...

META-STABILITY PREVENTION FOR OSCILLATORS

MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A...

Partially Depopulated Interconnection Arrays for Packaged Semicondu...

Complementary pass gate logic implementation of 64-bit arithmetic l...

Method for scan testing and clocking dynamic domino circuits in VLS...

Method to reduce leakage during a semi-conductor burn-in procedure