Barry K. Britton

Person

Schnecksville, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Field programmable gate array with write-port enabled memory
- Patent number 5,623,217
- Issue date Apr 22, 1997
- Lucent Technologies Inc.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-skew signal routing in a programmable array
- Patent number 5,528,170
- Issue date Jun 18, 1996
- AT&T Corp.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA with distributed switch matrix
- Patent number 5,396,126
- Issue date Mar 7, 1995
- AT&T Corp.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method to improve programming speed of field programm...
- Patent number 5,394,031
- Issue date Feb 28, 1995
- AT&T Corp.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable function unit with programmable fast ripple logic
- Patent number 5,386,156
- Issue date Jan 31, 1995
- AT&T Corp.
- Barry K. Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-skew signal routing in a programmable array
- Patent number 5,384,497
- Issue date Jan 24, 1995
- AT&T Corp.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA having PFU with programmable output driver inputs
- Patent number 5,381,058
- Issue date Jan 10, 1995
- AT&T Corp.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array with direct input/output connection
- Patent number 5,311,080
- Issue date May 10, 1994
- AT&T Bell Laboratories
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY

Barry K. Britton

Person

Patents Grantslast 30 patents

Field programmable gate array with write-port enabled memory

Low-skew signal routing in a programmable array

FPGA with distributed switch matrix

Apparatus and method to improve programming speed of field programm...

Programmable function unit with programmable fast ripple logic

Low-skew signal routing in a programmable array

FPGA having PFU with programmable output driver inputs

Field programmable gate array with direct input/output connection