Barry Wagner

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory management systems and methods
- Patent number 11,256,568
- Issue date Feb 22, 2022
- NVIDIA Corporation
- Bruce Lam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management systems and methods
- Patent number 10,528,423
- Issue date Jan 7, 2020
- NVIDIA Corporation
- Bruce Lam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller and a dynamic random access memory interface
- Patent number 8,738,852
- Issue date May 27, 2014
- NVIDIA Corporation
- Alok Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loopback configuration for bi-directional interfaces
- Patent number 8,724,483
- Issue date May 13, 2014
- NVIDIA Corporation
- Ting Sheng Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory device synchronization
- Patent number 8,495,327
- Issue date Jul 23, 2013
- NVIDIA Corporation
- Sean Jeffrey Treichler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for configurable digital communication
- Patent number 8,417,838
- Issue date Apr 9, 2013
- NVIDIA Corporation
- Anthony Michael Tamasi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable GPU and method for graphics processing using a configu...
- Patent number 8,412,872
- Issue date Apr 2, 2013
- NVIDIA Corporation
- Barry A. Wagner
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Apparatus, system, and method for graphics memory hub
- Patent number 8,194,085
- Issue date Jun 5, 2012
- NVIDIA Corporation
- Joseph David Greco
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Low latency synchronous memory performance switching
- Patent number 8,095,761
- Issue date Jan 10, 2012
- NVIDIA Corporation
- Hans Wolfgang Schulze
- G11 - INFORMATION STORAGE
Information Patent Grant
Low latency synchronous memory performance switching with drift ref...
- Patent number 8,095,762
- Issue date Jan 10, 2012
- NVIDIA Corporation
- Hans Wolfgang Schulze
- G11 - INFORMATION STORAGE
Information Patent Grant
Low latency synchronous memory performance switching using update c...
- Patent number 8,055,871
- Issue date Nov 8, 2011
- NVIDIA Corporation
- Hans Wolfgang Schulze
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer chassis with partitions for improved airflow
- Patent number 7,885,062
- Issue date Feb 8, 2011
- NVIDIA Corporation
- Barry A. Wagner
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Management of operation of an integrated circuit
- Patent number 7,761,191
- Issue date Jul 20, 2010
- NVIDIA Corporation
- Barry A. Wagner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory clock adjustments
- Patent number 7,657,775
- Issue date Feb 2, 2010
- NVIDIA Corporation
- Barry Wagner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management modes for memory devices
- Patent number 7,613,064
- Issue date Nov 3, 2009
- NVIDIA Corporation
- Barry A. Wagner
- G11 - INFORMATION STORAGE
Information Patent Grant
Data interface calibration
- Patent number 7,603,246
- Issue date Oct 13, 2009
- NVIDIA Corporation
- Russell R. Newcomb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary data encoding/decoding such as for communicating between com...
- Patent number 7,574,647
- Issue date Aug 11, 2009
- NVIDIA Corporation
- Russell R. Newcomb
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for dynamic power adjustment in a memory subsy...
- Patent number 7,548,481
- Issue date Jun 16, 2009
- NVIDIA Corp.
- Thomas E. Dewey
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for memory training concurrent with data trans...
- Patent number 7,532,218
- Issue date May 12, 2009
- NVIDIA Corporation
- Barry Wagner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary data encoding/decoding with error detection, such as for com...
- Patent number 7,519,892
- Issue date Apr 14, 2009
- NVIDIA Corporation
- Russell R. Newcomb
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus, system, and method for graphics memory hub
- Patent number 7,477,257
- Issue date Jan 13, 2009
- NVIDIA Corporation
- Joseph David Greco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device row and/or column access efficiency
- Patent number 7,447,848
- Issue date Nov 4, 2008
- Barry Wagner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data mask as write-training feedback flag
- Patent number 7,370,170
- Issue date May 6, 2008
- NVIDIA Corporation
- Ashfaq R. Shaikh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of providing a second clock while changing a first supplied...
- Patent number 7,315,957
- Issue date Jan 1, 2008
- NVIDIA Corporation
- Barry Wagner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for dynamic power supply voltage adjustment for a...
- Patent number 6,947,865
- Issue date Sep 20, 2005
- NVIDIA Corporation
- Ludger Mimberg
- G01 - MEASURING TESTING
Information Patent Grant
Memory system for use on a circuit board in which the number of loa...
- Patent number 6,496,404
- Issue date Dec 17, 2002
- NVIDIA Corporation
- Larry Fiedler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system for use on a circuit board in which the number of loa...
- Patent number 6,362,997
- Issue date Mar 26, 2002
- NVidia
- Larry Fiedler
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY MANAGEMENT SYSTEMS AND METHODS
- Publication number 20200089568
- Publication date Mar 19, 2020
- NVIDIA Corporation
- Bruce Lam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT SYSTEMS AND METHODS
- Publication number 20170153945
- Publication date Jun 1, 2017
- NVIDIA Corporation
- Bruce Lam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER AND A DYNAMIC RANDOM ACCESS MEMORY INTERFACE
- Publication number 20130054884
- Publication date Feb 28, 2013
- Alok GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE SYNCHRONIZATION
- Publication number 20110302385
- Publication date Dec 8, 2011
- NVIDIA Corporation
- Sean Jeffrey Treichler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Loopback configuration for bi-directional interfaces
- Publication number 20090103443
- Publication date Apr 23, 2009
- Ting Sheng Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus, System, and Method For Graphics Memory Hub
- Publication number 20090079748
- Publication date Mar 26, 2009
- NVIDIA Corporation
- Joseph David Greco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data interface calibration
- Publication number 20070239379
- Publication date Oct 11, 2007
- NVIDIA CORPORATION
- Russell R. Newcomb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for configurable digital communication
- Publication number 20070162624
- Publication date Jul 12, 2007
- Anthony Michael Tamasi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory device row and/or column access efficiency
- Publication number 20070156979
- Publication date Jul 5, 2007
- NVIDIA CORPORATION
- Barry Wagner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, system, and method for graphics memory hub
- Publication number 20070139426
- Publication date Jun 21, 2007
- Joseph David Greco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer chassis for improved airflow and heat transfer from comput...
- Publication number 20070133167
- Publication date Jun 14, 2007
- Barry A. Wagner
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Data mask as write-training feedback flag
- Publication number 20050240744
- Publication date Oct 27, 2005
- Ashfaq R. Shaikh
- G11 - INFORMATION STORAGE

Barry Wagner

Person

Patents Grantslast 30 patents

Memory management systems and methods

Memory management systems and methods

Memory controller and a dynamic random access memory interface

Loopback configuration for bi-directional interfaces

Memory device synchronization

System and method for configurable digital communication

Configurable GPU and method for graphics processing using a configu...

Apparatus, system, and method for graphics memory hub

Low latency synchronous memory performance switching

Low latency synchronous memory performance switching with drift ref...

Low latency synchronous memory performance switching using update c...

Computer chassis with partitions for improved airflow

Management of operation of an integrated circuit

Dynamic memory clock adjustments

Power management modes for memory devices

Data interface calibration

Binary data encoding/decoding such as for communicating between com...

Method and apparatus for dynamic power adjustment in a memory subsy...

Method and apparatus for memory training concurrent with data trans...

Binary data encoding/decoding with error detection, such as for com...

Apparatus, system, and method for graphics memory hub

Memory device row and/or column access efficiency

Data mask as write-training feedback flag

Method of providing a second clock while changing a first supplied...

Method and system for dynamic power supply voltage adjustment for a...

Memory system for use on a circuit board in which the number of loa...

Memory system for use on a circuit board in which the number of loa...

Patents Applicationslast 30 patents

MEMORY MANAGEMENT SYSTEMS AND METHODS

MEMORY MANAGEMENT SYSTEMS AND METHODS

MEMORY CONTROLLER AND A DYNAMIC RANDOM ACCESS MEMORY INTERFACE

MEMORY DEVICE SYNCHRONIZATION

Loopback configuration for bi-directional interfaces

Apparatus, System, and Method For Graphics Memory Hub

Data interface calibration

System and method for configurable digital communication

Memory device row and/or column access efficiency

Apparatus, system, and method for graphics memory hub

Computer chassis for improved airflow and heat transfer from comput...

Data mask as write-training feedback flag