Claims
- 1. A memory system comprising:a circuit board; and at least two memory devices mounted on the circuit board; each of the at least two memory devices including a plurality of pins for receiving and providing signals; each of the at least two memory devices being identical, wherein at least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other at least two memory devices such that a pin of the first portion coupled to a pin of the second portion forms a coupled load, wherein the coupled load appears as one load.
- 2. The memory system of claim 1 wherein the signals comprise address signals.
- 3. The memory system of claim 1 which includes a remapping device that is coupled to the at least two memory devices for ensuring that the appropriate pins are defined properly.
- 4. The memory system of claim 1 wherein the at least two memory devices are identical and disposed on opposite sides of the circuit board such that the pins on each of the at least two memory devices are mirror images of each other.
- 5. The memory system of claim 4 wherein a remapping device is coupled to the first and second memory devices for ensuring that the appropriate pins are defined properly.
- 6. The memory system of claim 5 wherein the remapping device comprises a look-up table.
- 7. The memory system of claim 6 wherein the remapping device comprises a multiplexor arrangement.
- 8. A memory system comprising:a circuit board; first and second memory devices mounted on the circuit board; each of the first and second memory devices including a plurality of pins for receiving and providing address signals; wherein the first and second memory devices are identical and disposed on opposite sides of the circuit board such that the pins on each of the first and second memory devices are mirror images of each other; wherein at least a first portion of the pins of one of the first memory device is coupled to at least a second portion of the pins of the second memory device such that a pin of the first portion coupled to a pin of the second portion forms a coupled load, wherein the coupled load appears as one load; and a remapping device is coupled to the first and second memory devices for ensuring that the appropriate pins are defined properly.
- 9. The memory system of claim 8 wherein the remapping device comprises a look-up table.
- 10. The memory system of claim 8 wherein the remapping device comprises a multiplexor arrangement.
- 11. A memory system comprising:a circuit board; and first and second memory devices mounted on the circuit board; each of the first and second memory devices including a plurality of pins for receiving and providing address signals; wherein the first and second memory devices are identical and disposed on opposite sides of the circuit board such that the pins on each of the first and second memory. devices are mirror images of each other; wherein at least a first portion of the pins of one of the first memory device is coupled to at least a second portion of the pins of the second memory device such that a pin of the first portion coupled to a pin of the second portion forms a coupled load, wherein the coupled load appears as one load.
- 12. A memory system comprising:a circuit board; and first and second memory devices mounted and positioned on opposite sides of the circuit board, each of the first and second memory devices including a plurality of pins, wherein a different pin from each of the first and second memory devices are coupled together to form a coupled load.
- 13. The memory system of claim 12 wherein the plurality of pins each of the first and second memory devices are mirror images of each other.
- 14. The memory system of claim 12 wherein the signals comprise address signals.
- 15. The memory system of claim 12 wherein a remapping device is coupled to the first and second memory devices for ensuring that the appropriate pins are defined properly.
- 16. The memory system of claim 15 wherein the remapping device comprises a look-up table.
- 17. The memory system of claim 15 wherein the remapping device comprises a multiplexor arrangement.
Parent Case Info
This application is a continuation of application Ser. No. 09/690,170 filed Oct. 6, 2000, now U.S. Pat. No. 6,362,997.
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Continuations (1)
|
Number |
Date |
Country |
Parent |
09/690170 |
Oct 2000 |
US |
Child |
09/993105 |
|
US |