Benjamin C. Chaffin

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performing instruction fetch pipeline synchronization (IFPS) in pro...
- Patent number 12,346,264
- Issue date Jul 1, 2025
- Ampere Computing LLC
- Bret Leslie Toll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigation of return stack buffer side channel attacks in a processor
- Patent number 12,333,001
- Issue date Jun 17, 2025
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, apparatus, and instructions for user-level thread suspension
- Patent number 12,020,031
- Issue date Jun 25, 2024
- Intel Corporation
- Michael Mishaeli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for run-time checking of memory tags...
- Patent number 11,586,537
- Issue date Feb 21, 2023
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, apparatus, and instructions for user level thread suspension
- Patent number 11,023,233
- Issue date Jun 1, 2021
- Intel Corporation
- Michael Mishaeli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stateless capture of data linear addresses during precise event bas...
- Patent number 10,175,986
- Issue date Jan 8, 2019
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for user-level thread synchronization with a m...
- Patent number 9,898,351
- Issue date Feb 20, 2018
- Intel Corporation
- Benjamin C. Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable event handling in multi-threaded processor cores
- Patent number 9,886,396
- Issue date Feb 6, 2018
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficiently managing architectural registe...
- Patent number 9,804,842
- Issue date Oct 31, 2017
- Intel Corporation
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory fault suppression via re-execution and hardware FSM
- Patent number 9,715,432
- Issue date Jul 25, 2017
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing TLB mappings between contexts
- Patent number 9,703,566
- Issue date Jul 11, 2017
- Intel Corporation
- Jonathan D. Combs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stateless capture of data linear addresses during precise event bas...
- Patent number 9,652,237
- Issue date May 16, 2017
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 8,671,275
- Issue date Mar 11, 2014
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 8,522,044
- Issue date Aug 27, 2013
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 8,458,464
- Issue date Jun 4, 2013
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to handle events in a machine with isolated execution
- Patent number 7,793,111
- Issue date Sep 7, 2010
- Intel Corporation
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microinstruction pointer stack including speculative pointers for o...
- Patent number 7,231,511
- Issue date Jun 12, 2007
- Intel Corporation
- Michael P. Cornaby
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR HANDLING CACHE UPDATES
- Publication number 20250130945
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Benjamin Crawford CHAFFIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR OPTIMIZING STORE OF COMMON VALUES TO MEMORY STRUCTURES
- Publication number 20250130804
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Jonathan Christopher PERRY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION FUSION
- Publication number 20250130809
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Benjamin Crawford CHAFFIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING ADDITIONAL OPERATIONS FOR A FUNCTIONAL UNIT OF A PROCESSO...
- Publication number 20250130798
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Benjamin Crawford CHAFFIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR MACRO-OPERATION FUSION
- Publication number 20250130807
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Benjamin Crawford CHAFFIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD OF WORKLOAD THROTTLING IN A MESH NETWORK
- Publication number 20250130852
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Benjamin Crawford CHAFFIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PERFORMING NON-VECTOR MICRO-OPERATIONS ON VECTOR HAR...
- Publication number 20250130799
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Christopher PALISTRANT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PRO...
- Publication number 20250130953
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Bret Leslie Toll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS EMPLOYING DEFAULT TAGS FOR WRITES TO MEMORY FROM DEVICES...
- Publication number 20250110902
- Publication date Apr 3, 2025
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS WITH TOGGLEABLE MEMORY TAGGING EXTENSIONS AND RELATED ME...
- Publication number 20250103506
- Publication date Mar 27, 2025
- Ampere Computing LLC
- Bret Leslie Toll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TRAINED SCALABLE PREFETCHER, AND RELATED METHODS
- Publication number 20240232090
- Publication date Jul 11, 2024
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATION OF RETURN STACK BUFFER SIDE CHANNEL ATTACKS IN A PROCESSOR
- Publication number 20220043908
- Publication date Feb 10, 2022
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR RUN-TIME CHECKING OF MEMORY TAGS...
- Publication number 20220043748
- Publication date Feb 10, 2022
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION
- Publication number 20210357214
- Publication date Nov 18, 2021
- Intel Corporation
- Michael Mishaeli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...
- Publication number 20170242698
- Publication date Aug 24, 2017
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION
- Publication number 20170228233
- Publication date Aug 10, 2017
- Intel Corporation
- Michael Mishaeli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for user-level thread synchronization with a m...
- Publication number 20170185458
- Publication date Jun 29, 2017
- Intel Corporation
- Benjamin C. Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM
- Publication number 20160179632
- Publication date Jun 23, 2016
- Intel Corporation
- Ramon MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES
- Publication number 20160179533
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTE...
- Publication number 20160179527
- Publication date Jun 23, 2016
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...
- Publication number 20160179541
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING TLB MAPPINGS BETWEEN CONTEXTS
- Publication number 20140223141
- Publication date Aug 7, 2014
- Jonathan D. Combs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION
- Publication number 20100332760
- Publication date Dec 30, 2010
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION
- Publication number 20100325354
- Publication date Dec 23, 2010
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION
- Publication number 20100325445
- Publication date Dec 23, 2010
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to modify a timer
- Publication number 20070260907
- Publication date Nov 8, 2007
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to handle events in a machine with isolated execution
- Publication number 20050283660
- Publication date Dec 22, 2005
- Francis X. McKeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microinstruction pointer stack in a processor
- Publication number 20030191929
- Publication date Oct 9, 2003
- Michael P. Cornaby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microinstruction sequencer stack
- Publication number 20020129229
- Publication date Sep 12, 2002
- Michael Cornaby
- G06 - COMPUTING CALCULATING COUNTING

Benjamin C. Chaffin

Person

Patents Grantslast 30 patents

Performing instruction fetch pipeline synchronization (IFPS) in pro...

Mitigation of return stack buffer side channel attacks in a processor

Methods, apparatus, and instructions for user-level thread suspension

Method, apparatus, and system for run-time checking of memory tags...

Methods, apparatus, and instructions for user level thread suspension

Stateless capture of data linear addresses during precise event bas...

Method and apparatus for user-level thread synchronization with a m...

Scalable event handling in multi-threaded processor cores

Method and apparatus for efficiently managing architectural registe...

Memory fault suppression via re-execution and hardware FSM

Sharing TLB mappings between contexts

Stateless capture of data linear addresses during precise event bas...

Mechanism to handle events in a machine with isolated execution

Mechanism to handle events in a machine with isolated execution

Mechanism to handle events in a machine with isolated execution

Mechanism to handle events in a machine with isolated execution

Microinstruction pointer stack including speculative pointers for o...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR HANDLING CACHE UPDATES

TECHNIQUES FOR OPTIMIZING STORE OF COMMON VALUES TO MEMORY STRUCTURES

MECHANISM FOR INSTRUCTION FUSION

PROVIDING ADDITIONAL OPERATIONS FOR A FUNCTIONAL UNIT OF A PROCESSO...

PROCESSOR MACRO-OPERATION FUSION

APPARATUS AND METHOD OF WORKLOAD THROTTLING IN A MESH NETWORK

TECHNIQUES FOR PERFORMING NON-VECTOR MICRO-OPERATIONS ON VECTOR HAR...

PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PRO...

PROCESSORS EMPLOYING DEFAULT TAGS FOR WRITES TO MEMORY FROM DEVICES...

PROCESSORS WITH TOGGLEABLE MEMORY TAGGING EXTENSIONS AND RELATED ME...

MULTI-TRAINED SCALABLE PREFETCHER, AND RELATED METHODS

MITIGATION OF RETURN STACK BUFFER SIDE CHANNEL ATTACKS IN A PROCESSOR

METHOD, APPARATUS, AND SYSTEM FOR RUN-TIME CHECKING OF MEMORY TAGS...

METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...

METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION

Method and apparatus for user-level thread synchronization with a m...

MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM

SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES

METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTE...

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...

SHARING TLB MAPPINGS BETWEEN CONTEXTS

MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION

MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION

MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION

Technique to modify a timer

Mechanism to handle events in a machine with isolated execution

Microinstruction pointer stack in a processor

Microinstruction sequencer stack