Bernard Aspar

Person

Riues, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Heterostructure and method of fabrication
- Patent number 12,101,080
- Issue date Sep 24, 2024
- SOITEC
- Arnaud Castex
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Heterostructure and method of fabrication
- Patent number 11,637,542
- Issue date Apr 25, 2023
- Soitec
- Arnaud Castex
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterostructure and method of fabrication
- Patent number 11,595,020
- Issue date Feb 28, 2023
- Soitec
- Arnaud Castex
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for radio frequency applications
- Patent number 11,502,428
- Issue date Nov 15, 2022
- Soitec
- Eric Desbonnets
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for radio frequency applications
- Patent number 11,043,756
- Issue date Jun 22, 2021
- Soitec
- Eric Desbonnets
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterostructure and method of fabrication
- Patent number 10,826,459
- Issue date Nov 3, 2020
- Soitec
- Arnaud Castex
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for fabrication of semiconductor structures using laser lif...
- Patent number 9,728,458
- Issue date Aug 8, 2017
- Soitec
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming semiconductor structures including MEMS devices...
- Patent number 9,511,996
- Issue date Dec 6, 2016
- Soitec
- Mariam Sadaka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Methods of forming semiconductor structures including MEMS devices...
- Patent number 9,481,566
- Issue date Nov 1, 2016
- Soitec
- Mariam Sadaka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Process of treating defects during the bonding of wafers
- Patent number 8,722,515
- Issue date May 13, 2014
- Soitec
- Chrystelle Lagahe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process for a stacked structure comprising a thin lay...
- Patent number 8,679,946
- Issue date Mar 25, 2014
- Commissariat a l'Energie Atomique et aux Energies Alternatives
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for trimming a structure obtained by the assembly of two plates
- Patent number 8,628,674
- Issue date Jan 14, 2014
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Marc Zussy
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Process for the transfer of a thin film comprising an inclusion cre...
- Patent number 8,609,514
- Issue date Dec 17, 2013
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for fabricating a semiconductor substrate
- Patent number 8,575,010
- Issue date Nov 5, 2013
- Soitec
- Alexis Drouin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of treating defects during the bonding of wafers
- Patent number 8,530,334
- Issue date Sep 10, 2013
- Soitec
- Chrystelle Lagahe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process for a stacked structure comprising a thin lay...
- Patent number 8,481,409
- Issue date Jul 9, 2013
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of making substrate structures having a weakened intermedia...
- Patent number 8,475,693
- Issue date Jul 2, 2013
- Soitec
- Michel Bruel
- B32 - LAYERED PRODUCTS
Information Patent Grant
Process for the transfer of a thin film comprising an inclusion cre...
- Patent number 8,470,712
- Issue date Jun 25, 2013
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for trimming a structure obtained by the assembly of two plates
- Patent number 8,329,048
- Issue date Dec 11, 2012
- Commissariat a l'Energie Atomique
- Marc Zussy
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of transferring a circuit onto a ground plane
- Patent number 8,298,915
- Issue date Oct 30, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Bernard Aspar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface roughening process
- Patent number 8,268,703
- Issue date Sep 18, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Bernard Aspar
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Process for assembling wafers by means of molecular adhesion
- Patent number 8,232,130
- Issue date Jul 31, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Marcel Broekaart
- C03 - GLASS MINERAL OR SLAG WOOL
Information Patent Grant
Stacked structure and production method thereof
- Patent number 8,193,069
- Issue date Jun 5, 2012
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Annealing process for annealing a structure
- Patent number 8,158,487
- Issue date Apr 17, 2012
- Soitec
- Nicolas Sousbie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing a thin layer of semiconductor material
- Patent number 8,101,503
- Issue date Jan 24, 2012
- Commissariat a l'Energie Atomique
- Bernard Aspar
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for producing partial SOI structures comprising zones connec...
- Patent number 8,044,465
- Issue date Oct 25, 2011
- S.O.I.TEC Solicon On Insulator Technologies
- Bernard Aspar
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Detachable substrate with controlled mechanical strength and method...
- Patent number 7,902,038
- Issue date Mar 8, 2011
- Commissariat a l'Energie Atomique
- Bernard Aspar
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Process for the transfer of a thin film
- Patent number 7,883,994
- Issue date Feb 8, 2011
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for transferring wafers
- Patent number 7,807,482
- Issue date Oct 5, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Bernard Aspar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of forming and controlling rough interfaces
- Patent number 7,807,548
- Issue date Oct 5, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Bernard Aspar
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
HETEROSTRUCTURE AND METHOD OF FABRICATION
- Publication number 20230275559
- Publication date Aug 31, 2023
- SOITEC
- Arnaud Castex
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STRUCTURE FOR RADIO FREQUENCY APPLICATIONS
- Publication number 20220368036
- Publication date Nov 17, 2022
- SOITEC
- Eric Desbonnets
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR RADIO FREQUENCY APPLICATIONS
- Publication number 20210280990
- Publication date Sep 9, 2021
- SOITEC
- Eric Desbonnets
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROSTRUCTURE AND METHOD OF FABRICATION
- Publication number 20210058058
- Publication date Feb 25, 2021
- SOITEC
- Arnaud Castex
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROSTRUCTURE AND METHOD OF FABRICATION
- Publication number 20200280298
- Publication date Sep 3, 2020
- SOITEC
- Arnaud Castex
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR A RADIO FREQUENCY APPLICATION
- Publication number 20190372243
- Publication date Dec 5, 2019
- SOITEC
- Eric Desbonnets
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROSTRUCTURE AND METHOD OF FABRICATION
- Publication number 20180159498
- Publication date Jun 7, 2018
- SOITEC
- Arnaud Castex
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES...
- Publication number 20150210540
- Publication date Jul 30, 2015
- SOITEC
- Mariam Sadaka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES...
- Publication number 20150191344
- Publication date Jul 9, 2015
- SOITEC
- Mariam Sadaka
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES USING LASER LIF...
- Publication number 20150179520
- Publication date Jun 25, 2015
- SOITEC
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS
- Publication number 20130323861
- Publication date Dec 5, 2013
- SOITEC
- Chrystelle Lagahe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR THE TRANSFER OF A THIN FILM COMPRISING AN INCLUSION CRE...
- Publication number 20130273713
- Publication date Oct 17, 2013
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING PROCESS FOR A STACKED STRUCTURE COMPRISING A THIN LAY...
- Publication number 20130230967
- Publication date Sep 5, 2013
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR TRIMMING A STRUCTURE OBTAINED BY THE ASSEMBLY OF TWO PLATES
- Publication number 20130078785
- Publication date Mar 28, 2013
- COMMISSARIAT A L'ENERGIE ATOMIQUE
- Marc Zussy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PR...
- Publication number 20130012024
- Publication date Jan 10, 2013
- SOITEC
- Bernard Aspar
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF PRODUCING A THIN LAYER OF SEMICONDUCTOR MATERIAL
- Publication number 20120133028
- Publication date May 31, 2012
- COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA)
- Bernard Aspar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHODS OF MAKING SUBSTRATE STRUCTURES HAVING A WEAKENED INTERMEDIA...
- Publication number 20110250416
- Publication date Oct 13, 2011
- Michel Bruel
- B32 - LAYERED PRODUCTS
Information Patent Application
ANNEALING PROCESS FOR ANNEALING A STRUCTURE
- Publication number 20110183495
- Publication date Jul 28, 2011
- Nicolas Sousbie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR THE TRANSFER OF A THIN FILM COMPRISING AN INCLUSION CRE...
- Publication number 20110092051
- Publication date Apr 21, 2011
- COMMISSARIAT A L'ENERGIE ATOMIQUE
- Hubert Moriceau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE
- Publication number 20110024868
- Publication date Feb 3, 2011
- Alexis Drouin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS
- Publication number 20100285213
- Publication date Nov 11, 2010
- S.O.I.Tec Silicon on Insulator Technologies
- Chrystelle Lagahe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING PARTIAL SOI STRUCTURES COMPRISING ZONES CONNEC...
- Publication number 20100176397
- Publication date Jul 15, 2010
- TRACIT TECHNOLOGIES
- Bernard ASPAR
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD FOR PRODUCING SELF-SUPPORTING MEMBRANES
- Publication number 20100032085
- Publication date Feb 11, 2010
- Nicolas Sousbie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compliant Substrate In Particular For Hetero-Epitaxial Depositing
- Publication number 20090311477
- Publication date Dec 17, 2009
- Bernard ASPAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Making a Plate-Like Detachable Structure, in Particular...
- Publication number 20090301995
- Publication date Dec 10, 2009
- TRACIT TECHNOLOGIES
- Bernard Aspar
- C30 - CRYSTAL GROWTH
Information Patent Application
Process for assembling wafers by means of molecular adhesion
- Publication number 20090280595
- Publication date Nov 12, 2009
- S.O.I. TEC Silicon on Insulator Technologies
- Marcel Broekaart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR THE COLLECTIVE FABRICATION OF MICROSTRUCTURES CONSISTIN...
- Publication number 20090275152
- Publication date Nov 5, 2009
- E2V Semiconductors
- Philippe Rommeveaux
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF PRODUCING A THIN LAYER OF SEMICONDUCTOR MATERIAL
- Publication number 20090130392
- Publication date May 21, 2009
- COMMISSARIAT A L'ENERGIE ATOMIQUE (CEA)
- Bernard Aspar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD FOR TRIMMING A STRUCTURE OBTAINED BY THE ASSEMBLY OF TWO PLATES
- Publication number 20090095399
- Publication date Apr 16, 2009
- COMMISSARIAT A L'ENERGIE ATOMIQUE
- Marc Zussy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Transferring Wafers
- Publication number 20080254596
- Publication date Oct 16, 2008
- TRACIT TECHNOLOGIES
- Bernard Aspar
- H01 - BASIC ELECTRIC ELEMENTS

Bernard Aspar

Person

Patents Grantslast 30 patents

Heterostructure and method of fabrication

Heterostructure and method of fabrication

Heterostructure and method of fabrication

Structure for radio frequency applications

Structure for radio frequency applications

Heterostructure and method of fabrication

Methods for fabrication of semiconductor structures using laser lif...

Methods of forming semiconductor structures including MEMS devices...

Methods of forming semiconductor structures including MEMS devices...

Process of treating defects during the bonding of wafers

Manufacturing process for a stacked structure comprising a thin lay...

Method for trimming a structure obtained by the assembly of two plates

Process for the transfer of a thin film comprising an inclusion cre...

Method for fabricating a semiconductor substrate

Process of treating defects during the bonding of wafers

Manufacturing process for a stacked structure comprising a thin lay...

Methods of making substrate structures having a weakened intermedia...

Process for the transfer of a thin film comprising an inclusion cre...

Method for trimming a structure obtained by the assembly of two plates

Method of transferring a circuit onto a ground plane

Surface roughening process

Process for assembling wafers by means of molecular adhesion

Stacked structure and production method thereof

Annealing process for annealing a structure

Method of producing a thin layer of semiconductor material

Method for producing partial SOI structures comprising zones connec...

Detachable substrate with controlled mechanical strength and method...

Process for the transfer of a thin film

Method for transferring wafers

Process of forming and controlling rough interfaces

Patents Applicationslast 30 patents

HETEROSTRUCTURE AND METHOD OF FABRICATION

STRUCTURE FOR RADIO FREQUENCY APPLICATIONS

STRUCTURE FOR RADIO FREQUENCY APPLICATIONS

HETEROSTRUCTURE AND METHOD OF FABRICATION

HETEROSTRUCTURE AND METHOD OF FABRICATION

STRUCTURE FOR A RADIO FREQUENCY APPLICATION

HETEROSTRUCTURE AND METHOD OF FABRICATION

METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES...

METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES...

METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES USING LASER LIF...

PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS

PROCESS FOR THE TRANSFER OF A THIN FILM COMPRISING AN INCLUSION CRE...

MANUFACTURING PROCESS FOR A STACKED STRUCTURE COMPRISING A THIN LAY...

METHOD FOR TRIMMING A STRUCTURE OBTAINED BY THE ASSEMBLY OF TWO PLATES

STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PR...

METHOD OF PRODUCING A THIN LAYER OF SEMICONDUCTOR MATERIAL

METHODS OF MAKING SUBSTRATE STRUCTURES HAVING A WEAKENED INTERMEDIA...

ANNEALING PROCESS FOR ANNEALING A STRUCTURE

PROCESS FOR THE TRANSFER OF A THIN FILM COMPRISING AN INCLUSION CRE...

METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE

PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS

METHOD FOR PRODUCING PARTIAL SOI STRUCTURES COMPRISING ZONES CONNEC...

METHOD FOR PRODUCING SELF-SUPPORTING MEMBRANES

Compliant Substrate In Particular For Hetero-Epitaxial Depositing

Method for Making a Plate-Like Detachable Structure, in Particular...

Process for assembling wafers by means of molecular adhesion

PROCESS FOR THE COLLECTIVE FABRICATION OF MICROSTRUCTURES CONSISTIN...

METHOD OF PRODUCING A THIN LAYER OF SEMICONDUCTOR MATERIAL

METHOD FOR TRIMMING A STRUCTURE OBTAINED BY THE ASSEMBLY OF TWO PLATES

Method for Transferring Wafers