Bich-Yen Nguyen

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing a CFET device
- Patent number 11,876,020
- Issue date Jan 16, 2024
- Soitec
- Walter Schwarzenbach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a structure for forming a tridimensional m...
- Patent number 11,205,702
- Issue date Dec 21, 2021
- Soitec
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor structure
- Patent number 11,156,778
- Issue date Oct 26, 2021
- Soitec
- Bich-Yen Nguyen
- G02 - OPTICS
Information Patent Grant
Method for fabrication of a semiconductor structure including an in...
- Patent number 11,114,314
- Issue date Sep 7, 2021
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a high-resistivity semiconductor-on-insula...
- Patent number 10,002,882
- Issue date Jun 19, 2018
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for radiofrequency applications and process for manufactu...
- Patent number 9,824,915
- Issue date Nov 21, 2017
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor structures including fin struc...
- Patent number 9,818,874
- Issue date Nov 14, 2017
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor layers including transistor ch...
- Patent number 9,576,798
- Issue date Feb 21, 2017
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-inverter circuit with multiple independent gate transistors
- Patent number 9,496,877
- Issue date Nov 15, 2016
- Soitec
- Carlos Mazure
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for fabricating semiconductor structures including fin struc...
- Patent number 9,349,865
- Issue date May 24, 2016
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming three-dimensionally integrated semiconductor sys...
- Patent number 9,293,448
- Issue date Mar 22, 2016
- Soitec
- Bich-Yen Nguyen
- G02 - OPTICS
Information Patent Grant
Method for fabricating semiconductor structures including fin struc...
- Patent number 9,219,150
- Issue date Dec 22, 2015
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor layers including transistor ch...
- Patent number 9,209,301
- Issue date Dec 8, 2015
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer with intrinsic semiconductor layer
- Patent number 9,177,961
- Issue date Nov 3, 2015
- Soitec
- Nicolas Daval
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor structures including transisto...
- Patent number 9,165,945
- Issue date Oct 20, 2015
- Soitec
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor substrate
- Patent number 9,035,474
- Issue date May 19, 2015
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a Ge on III/V-on-insulator structure
- Patent number 9,018,678
- Issue date Apr 28, 2015
- Soitec
- Nicolas Daval
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded semiconductor structures and method of forming same
- Patent number 8,987,114
- Issue date Mar 24, 2015
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming three dimensionally integrated semiconductor sys...
- Patent number 8,842,945
- Issue date Sep 23, 2014
- Soitec
- Bich-Yen Nguyen
- G02 - OPTICS
Information Patent Grant
Methods of forming bonded semiconductor structures including interc...
- Patent number 8,728,863
- Issue date May 20, 2014
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-inverter circuit on SeOI
- Patent number 8,654,602
- Issue date Feb 18, 2014
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-layer structures and process for fabricating semiconductor de...
- Patent number 8,652,887
- Issue date Feb 18, 2014
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-sense amplifier
- Patent number 8,625,374
- Issue date Jan 7, 2014
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of forming bonded semiconductor structures in 3D integratio...
- Patent number 8,617,925
- Issue date Dec 31, 2013
- Soitec
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM-type memory cell
- Patent number 8,575,697
- Issue date Nov 5, 2013
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Device comprising a field-effect transistor in a silicon-on-insulator
- Patent number 8,455,938
- Issue date Jun 4, 2013
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-sense amplifier
- Patent number 8,358,552
- Issue date Jan 22, 2013
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Power MOSFET with a gate structure of different material
- Patent number 8,309,410
- Issue date Nov 13, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Daniel T. Pham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-inverter circuit on SeOI
- Patent number 8,223,582
- Issue date Jul 17, 2012
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified hybrid orientation technology
- Patent number 8,125,032
- Issue date Feb 28, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
COMPLEMENTARY FIELD-EFFECT TRANSISTOR DEVICE INCLUDING AT LEAST ONE...
- Publication number 20240145314
- Publication date May 2, 2024
- SOITEC
- Walter Schwarzenbach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SeOI INTEGRATED CIRCUIT CHIP
- Publication number 20230170264
- Publication date Jun 1, 2023
- SOITEC
- Trong Hyunh-Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
- Publication number 20230129131
- Publication date Apr 27, 2023
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ARCHITECTURES WITH TENSILE AND COMPRESSIVE STRAINED SUBSTRATES
- Publication number 20220399441
- Publication date Dec 15, 2022
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS...
- Publication number 20220076993
- Publication date Mar 10, 2022
- SOITEC
- Yvan Morandini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS
- Publication number 20220076992
- Publication date Mar 10, 2022
- SOITEC
- Yvan Morandini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A CFET DEVICE
- Publication number 20210202326
- Publication date Jul 1, 2021
- SOITEC
- Walter Schwarzenbach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATION OF A SEMICONDUCTOR STRUCTURE INCLUDING AN IN...
- Publication number 20200328094
- Publication date Oct 15, 2020
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL M...
- Publication number 20200295138
- Publication date Sep 17, 2020
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
- Publication number 20190187376
- Publication date Jun 20, 2019
- SOITEC
- Bich-Yen Nguyen
- G02 - OPTICS
Information Patent Application
STRUCTURE FOR RADIOFREQUENCY APPLICATIONS AND PROCESS FOR MANUFACTU...
- Publication number 20170084478
- Publication date Mar 23, 2017
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A HIGH-RESISTIVITY SEMICONDUCTOR-ON-INSULA...
- Publication number 20160372484
- Publication date Dec 22, 2016
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUC...
- Publication number 20160268430
- Publication date Sep 15, 2016
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUC...
- Publication number 20160087100
- Publication date Mar 24, 2016
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING TRANSISTO...
- Publication number 20160086974
- Publication date Mar 24, 2016
- SOITEC
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR LAYERS INCLUDING TRANSISTOR CH...
- Publication number 20160086803
- Publication date Mar 24, 2016
- SOITEC
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING THREE-DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYS...
- Publication number 20140369646
- Publication date Dec 18, 2014
- Bich-Yen Nguyen
- G02 - OPTICS
Information Patent Application
PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS
- Publication number 20140225648
- Publication date Aug 14, 2014
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
NANO-SENSE AMPLIFIER
- Publication number 20130100749
- Publication date Apr 25, 2013
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATIO...
- Publication number 20130037960
- Publication date Feb 14, 2013
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Mariam Sadaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYSTEMS INCLUDING PHOT...
- Publication number 20130039615
- Publication date Feb 14, 2013
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Bich-Yen Nguyen
- G02 - OPTICS
Information Patent Application
METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING INTERC...
- Publication number 20130037959
- Publication date Feb 14, 2013
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME
- Publication number 20130015442
- Publication date Jan 17, 2013
- SOITEC
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-INVERTER CIRCUIT ON SeOI
- Publication number 20120250444
- Publication date Oct 4, 2012
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
WAFER WITH INTRINSIC SEMICONDUCTOR LAYER
- Publication number 20120228689
- Publication date Sep 13, 2012
- SOITEC
- Nicolas Daval
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE
- Publication number 20120228672
- Publication date Sep 13, 2012
- SOITEC
- Nicolas Daval
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DE...
- Publication number 20120231606
- Publication date Sep 13, 2012
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR
- Publication number 20110260233
- Publication date Oct 27, 2011
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE
- Publication number 20110241157
- Publication date Oct 6, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-INVERTER CIRCUIT ON SeO1
- Publication number 20110242926
- Publication date Oct 6, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE

Bich-Yen Nguyen

Person

Patents Grantslast 30 patents

Method for manufacturing a CFET device

Method for manufacturing a structure for forming a tridimensional m...

Method for manufacturing a semiconductor structure

Method for fabrication of a semiconductor structure including an in...

Method for manufacturing a high-resistivity semiconductor-on-insula...

Structure for radiofrequency applications and process for manufactu...

Method for fabricating semiconductor structures including fin struc...

Method for fabricating semiconductor layers including transistor ch...

Pseudo-inverter circuit with multiple independent gate transistors

Method for fabricating semiconductor structures including fin struc...

Methods of forming three-dimensionally integrated semiconductor sys...

Method for fabricating semiconductor structures including fin struc...

Method for fabricating semiconductor layers including transistor ch...

Wafer with intrinsic semiconductor layer

Method for fabricating semiconductor structures including transisto...

Method for manufacturing a semiconductor substrate

Method for forming a Ge on III/V-on-insulator structure

Bonded semiconductor structures and method of forming same

Methods of forming three dimensionally integrated semiconductor sys...

Methods of forming bonded semiconductor structures including interc...

Pseudo-inverter circuit on SeOI

Multi-layer structures and process for fabricating semiconductor de...

Nano-sense amplifier

Methods of forming bonded semiconductor structures in 3D integratio...

SRAM-type memory cell

Device comprising a field-effect transistor in a silicon-on-insulator

Nano-sense amplifier

Power MOSFET with a gate structure of different material

Pseudo-inverter circuit on SeOI

Modified hybrid orientation technology

Patents Applicationslast 30 patents

COMPLEMENTARY FIELD-EFFECT TRANSISTOR DEVICE INCLUDING AT LEAST ONE...

METHOD FOR MANUFACTURING A SeOI INTEGRATED CIRCUIT CHIP

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

DEVICE ARCHITECTURES WITH TENSILE AND COMPRESSIVE STRAINED SUBSTRATES

SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS...

SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS

METHOD FOR MANUFACTURING A CFET DEVICE

METHOD FOR FABRICATION OF A SEMICONDUCTOR STRUCTURE INCLUDING AN IN...

METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL M...

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

STRUCTURE FOR RADIOFREQUENCY APPLICATIONS AND PROCESS FOR MANUFACTU...

METHOD FOR MANUFACTURING A HIGH-RESISTIVITY SEMICONDUCTOR-ON-INSULA...

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUC...

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUC...

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING TRANSISTO...

METHOD FOR FABRICATING SEMICONDUCTOR LAYERS INCLUDING TRANSISTOR CH...

METHODS OF FORMING THREE-DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYS...

PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS

NANO-SENSE AMPLIFIER

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATIO...

THREE DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYSTEMS INCLUDING PHOT...

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING INTERC...

BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME

PSEUDO-INVERTER CIRCUIT ON SeOI

WAFER WITH INTRINSIC SEMICONDUCTOR LAYER

METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE

MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DE...

DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR

METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE

PSEUDO-INVERTER CIRCUIT ON SeO1