Bin Li

Person

Chantilly, VA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Radiation-hardened D flip-flop circuit
- Patent number 10,998,890
- Issue date May 4, 2021
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatuses for implementing cold-sparable SerDes
- Patent number 10,624,246
- Issue date Apr 14, 2020
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Current-mode-logic devices resistant to single event disturbances
- Patent number 8,928,348
- Issue date Jan 6, 2015
- BAE Systems Information and Electronic Systems Integration Inc.
- Patrick Fleming
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single-event upset hardened ring oscillator
- Patent number 8,547,178
- Issue date Oct 1, 2013
- BAE Systems Information and Electronic Systems Integration Inc.
- Neil E. Wood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustable write pulse generator within a chalcogenide memory device
- Patent number 8,059,454
- Issue date Nov 15, 2011
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Write circuit for providing distinctive write currents to a chalcog...
- Patent number 8,027,191
- Issue date Sep 27, 2011
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Analog access circuit for validating chalcogenide memory cells
- Patent number 7,986,550
- Issue date Jul 26, 2011
- BAE Systems Information and Electronics Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Hardened current mode logic (CML) voter circuit, system and method
- Patent number 7,965,098
- Issue date Jun 21, 2011
- BAE Systems Information and Electronic Systems Integration Inc.
- Neil Wood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-volatile single-event upset tolerant latch circuit
- Patent number 7,965,541
- Issue date Jun 21, 2011
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Read reference circuit for a sense amplifier within a chalcogenide...
- Patent number 7,916,527
- Issue date Mar 29, 2011
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/write circuit for accessing chalcogenide non-volatile memory c...
- Patent number 7,099,187
- Issue date Aug 29, 2006
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/write circuit for accessing chalcogenide non-volatile memory c...
- Patent number 6,965,521
- Issue date Nov 15, 2005
- BAE Systems, Information and Electronics Systems Integration, Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for accessing a chalcogenide memory array
- Patent number 6,944,041
- Issue date Sep 13, 2005
- BAE Systems Information and Electronic Systems Integration, Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for filtering single event effect (see) induced glitches
- Patent number 6,392,474
- Issue date May 21, 2002
- BAE Systems Information and Electronic Systems Integration Inc.
- Bin Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single event upset (SEU) hardened latch circuit
- Patent number 6,327,176
- Issue date Dec 4, 2001
- Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for hardening a static random access memory ce...
- Patent number 6,285,580
- Issue date Sep 4, 2001
- BAE Systems Information
- Ho Gia Phan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplexor having a single event upset (SEU) immune data keeper ci...
- Patent number 6,282,140
- Issue date Aug 28, 2001
- Systems Integration Inc.
- Ho Gia Phan
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced single event upset immune latch circuit
- Patent number 6,275,080
- Issue date Aug 14, 2001
- BAE Systems
- Ho G. Phan
- G11 - INFORMATION STORAGE
Information Patent Grant
Single event upset (SEU) hardened static random access memory cell
- Patent number 6,259,643
- Issue date Jul 10, 2001
- Systems Integration Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-restoring single event upset (SEU) hardened multiport memory cell
- Patent number 6,215,694
- Issue date Apr 10, 2001
- Lockheed Martin Corporation
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Single event upset (SEU) hardened static random access memory cell
- Patent number 6,208,554
- Issue date Mar 27, 2001
- Lockheed Martin Corporation
- Ho Gia Phan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
RADIATION-HARDENED D FLIP-FLOP CIRCUIT
- Publication number 20210257999
- Publication date Aug 19, 2021
- BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC
- Bin Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RADIATION-HARDENED D FLIP-FLOP CIRCUIT
- Publication number 20190363699
- Publication date Nov 28, 2019
- Bin Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUSES FOR IMPLEMENTING COLD-SPARABLE SERDES
- Publication number 20190045675
- Publication date Feb 7, 2019
- BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC
- Bin Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Single-Event Upset Hardened Ring Oscillator
- Publication number 20120154058
- Publication date Jun 21, 2012
- Neil E. Wood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HARDENED CURRENT MODE LOGIC (CML) VOTER CIRCUIT, SYSTEM AND METHOD
- Publication number 20100141296
- Publication date Jun 10, 2010
- BAE Systems Information and Electronics System Intergration, Inc.
- Neil Wood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable Write Pulse Generator Within a Chalcogenide Memory Device
- Publication number 20100135070
- Publication date Jun 3, 2010
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
Analog Access Circuit for Validating Chalcogenide Memory Cells
- Publication number 20100074000
- Publication date Mar 25, 2010
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
Write Circuit for Providing Distinctive Write Currents to a Chalcog...
- Publication number 20100039857
- Publication date Feb 18, 2010
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Single-Event Upset Tolerant Latch Circuit
- Publication number 20100027321
- Publication date Feb 4, 2010
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
Read Reference Circuit for a Sense Amplifier Within a Chalcogenide...
- Publication number 20100002500
- Publication date Jan 7, 2010
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
Read/write circuit for accessing chalcogenide non-volatile memory c...
- Publication number 20060013037
- Publication date Jan 19, 2006
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT FOR ACCESSING A CHALCOGENIDE MEMORY ARRAY
- Publication number 20050213367
- Publication date Sep 29, 2005
- BAE Systems Information and Electronic Systems Integration, Inc.
- Bin Li
- G11 - INFORMATION STORAGE
Information Patent Application
Read/write circuit for accessing chalcogenide non-volatile memory c...
- Publication number 20050024922
- Publication date Feb 3, 2005
- BAE SYSTEMS Information and Electronic Systems Integration, Inc
- Bin Li
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Radiation-hardened D flip-flop circuit

Apparatuses for implementing cold-sparable SerDes

Current-mode-logic devices resistant to single event disturbances

Single-event upset hardened ring oscillator

Adjustable write pulse generator within a chalcogenide memory device

Write circuit for providing distinctive write currents to a chalcog...

Analog access circuit for validating chalcogenide memory cells

Hardened current mode logic (CML) voter circuit, system and method

Non-volatile single-event upset tolerant latch circuit

Read reference circuit for a sense amplifier within a chalcogenide...

Read/write circuit for accessing chalcogenide non-volatile memory c...

Read/write circuit for accessing chalcogenide non-volatile memory c...

Circuit for accessing a chalcogenide memory array

Circuit for filtering single event effect (see) induced glitches

Single event upset (SEU) hardened latch circuit

Method and apparatus for hardening a static random access memory ce...

Multiplexor having a single event upset (SEU) immune data keeper ci...

Enhanced single event upset immune latch circuit

Single event upset (SEU) hardened static random access memory cell

Self-restoring single event upset (SEU) hardened multiport memory cell

Single event upset (SEU) hardened static random access memory cell

Patents Applicationslast 30 patents

RADIATION-HARDENED D FLIP-FLOP CIRCUIT

RADIATION-HARDENED D FLIP-FLOP CIRCUIT

APPARATUSES FOR IMPLEMENTING COLD-SPARABLE SERDES

Single-Event Upset Hardened Ring Oscillator

HARDENED CURRENT MODE LOGIC (CML) VOTER CIRCUIT, SYSTEM AND METHOD

Adjustable Write Pulse Generator Within a Chalcogenide Memory Device

Analog Access Circuit for Validating Chalcogenide Memory Cells

Write Circuit for Providing Distinctive Write Currents to a Chalcog...

Non-Volatile Single-Event Upset Tolerant Latch Circuit

Read Reference Circuit for a Sense Amplifier Within a Chalcogenide...

Read/write circuit for accessing chalcogenide non-volatile memory c...

CIRCUIT FOR ACCESSING A CHALCOGENIDE MEMORY ARRAY

Read/write circuit for accessing chalcogenide non-volatile memory c...