Bo Jin

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of ono integration into logic CMOS flow
- Patent number 12,048,162
- Issue date Jul 23, 2024
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Krishnaswamy Ramkumar
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of ono integration into logic CMOS flow
- Patent number 11,569,254
- Issue date Jan 31, 2023
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Krishnaswamy Ramkumar
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of ONO integration into logic CMOS flow
- Patent number 10,700,083
- Issue date Jun 30, 2020
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems, methods, and apparatus for memory cells with common source...
- Patent number 10,192,622
- Issue date Jan 29, 2019
- Cypress Semiconductor Corporation
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems, methods, and apparatus for memory cells with common source...
- Patent number 9,818,484
- Issue date Nov 14, 2017
- Cypress Semiconductor Corporation
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems, methods, and apparatus for memory cells with common source...
- Patent number 9,627,073
- Issue date Apr 18, 2017
- Cypress Semiconductor Corporation
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems, methods, and apparatus for memory cells with common source...
- Patent number 9,466,374
- Issue date Oct 11, 2016
- Cypress Semiconductor Corporation
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method of operating the same
- Patent number 9,355,725
- Issue date May 31, 2016
- Cypress Semiconductor Corporation
- Bo Jin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of ONO integration into logic CMOS flow
- Patent number 9,102,522
- Issue date Aug 11, 2015
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Simultaneously forming a dielectric layer in MOS and ONO device reg...
- Patent number 9,023,707
- Issue date May 5, 2015
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems, methods, and apparatus for memory cells with common source...
- Patent number 8,953,380
- Issue date Feb 10, 2015
- Cypress Semiconductor Corporation
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of ONO integration into MOS flow
- Patent number 8,071,453
- Issue date Dec 6, 2011
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Soft error resistant memory cell and method of manufacture
- Patent number 7,355,880
- Issue date Apr 8, 2008
- Cypress Semiconductor Corporation
- Bo Jin
- G11 - INFORMATION STORAGE
Information Patent Grant
Proble for testing integrated circuits
- Patent number 7,112,974
- Issue date Sep 26, 2006
- Cypress Semiconductor Corporation
- Bo Jin
- G01 - MEASURING TESTING
Information Patent Grant
Advanced probe card and method of fabricating same
- Patent number 7,112,975
- Issue date Sep 26, 2006
- Cypress Semiconductor Corporation
- Bo Jin
- G01 - MEASURING TESTING
Information Patent Grant
Probe card with an adapter layer for testing integrated circuits
- Patent number 6,847,218
- Issue date Jan 25, 2005
- Cypress Semiconductor Corporation
- James E. Nulty
- G01 - MEASURING TESTING
Information Patent Grant
Method for improving dielectric polishing
- Patent number 6,844,237
- Issue date Jan 18, 2005
- Cypress Semiconductor Corporation
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for shallow trench isolation and shallow trench isolation st...
- Patent number 6,825,544
- Issue date Nov 30, 2004
- Cypress Semiconductor Corporation
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for monitoring a semiconductor process, and me...
- Patent number 6,808,944
- Issue date Oct 26, 2004
- Cypress Semiconductor Corporation
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lot-optimized wafer level burn-in
- Patent number 6,800,495
- Issue date Oct 5, 2004
- Cypress Semiconductor Corporation
- Cesar Payan
- G01 - MEASURING TESTING
Information Patent Grant
Array of dice for testing integrated circuits
- Patent number 6,759,865
- Issue date Jul 6, 2004
- Cypress Semiconductor Corporation
- Qi Gu
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor structure and method of making contacts in a semicond...
- Patent number 6,734,108
- Issue date May 11, 2004
- Cypress Semiconductor Corporation
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of uniform polish in shallow trench isolation process
- Patent number 6,593,208
- Issue date Jul 15, 2003
- Cypress Semiconductor Corp.
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell design
- Patent number 6,534,805
- Issue date Mar 18, 2003
- Cypress Semiconductor Corp.
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Content addressable memory cell
- Patent number 6,480,406
- Issue date Nov 12, 2002
- Cypress Semiconductor Corp.
- Bo Jin
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method for making a notched transistor with spacers
- Patent number 6,461,904
- Issue date Oct 8, 2002
- Cypress Semiconductor Corp.
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method of making contacts and source an...
- Patent number 6,350,665
- Issue date Feb 26, 2002
- Cypress Semiconductor Corporation
- Bo Jin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW
- Publication number 20230209830
- Publication date Jun 29, 2023
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Krishnaswamy Ramkumar
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW
- Publication number 20210188629
- Publication date Jun 24, 2021
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Krishnaswamy Ramkumar
- B82 - NANO-TECHNOLOGY
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...
- Publication number 20190318785
- Publication date Oct 17, 2019
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...
- Publication number 20180082746
- Publication date Mar 22, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...
- Publication number 20170278573
- Publication date Sep 28, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...
- Publication number 20170011800
- Publication date Jan 12, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...
- Publication number 20150287464
- Publication date Oct 8, 2015
- CYPRESS SEMICONDUCTOR CORPORATION
- Xiaojun Yu
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY AND METHOD OF OPERATING THE SAME
- Publication number 20150170744
- Publication date Jun 18, 2015
- CYPRESS SEMICONDUCTOR CORPORATION
- Bo Jin
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW
- Publication number 20130178030
- Publication date Jul 11, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Krishnaswamy Ramkumar
- B82 - NANO-TECHNOLOGY
Information Patent Application
Lot-optimized wafer level burn-in
- Publication number 20040058461
- Publication date Mar 25, 2004
- Cesar Payan
- G01 - MEASURING TESTING

Person

Patents Grantslast 30 patents

Method of ono integration into logic CMOS flow

Method of ono integration into logic CMOS flow

Method of ONO integration into logic CMOS flow

Systems, methods, and apparatus for memory cells with common source...

Systems, methods, and apparatus for memory cells with common source...

Systems, methods, and apparatus for memory cells with common source...

Systems, methods, and apparatus for memory cells with common source...

Non-volatile memory and method of operating the same

Method of ONO integration into logic CMOS flow

Simultaneously forming a dielectric layer in MOS and ONO device reg...

Systems, methods, and apparatus for memory cells with common source...

Method of ONO integration into MOS flow

Soft error resistant memory cell and method of manufacture

Proble for testing integrated circuits

Advanced probe card and method of fabricating same

Probe card with an adapter layer for testing integrated circuits

Method for improving dielectric polishing

Method for shallow trench isolation and shallow trench isolation st...

Structure and method for monitoring a semiconductor process, and me...

Lot-optimized wafer level burn-in

Array of dice for testing integrated circuits

Semiconductor structure and method of making contacts in a semicond...

Method of uniform polish in shallow trench isolation process

SRAM cell design

Content addressable memory cell

Structure and method for making a notched transistor with spacers

Semiconductor structure and method of making contacts and source an...

Patents Applicationslast 30 patents

METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW

METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE...

NON-VOLATILE MEMORY AND METHOD OF OPERATING THE SAME

METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW

Lot-optimized wafer level burn-in