Boon Teik Chan

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
FET device and a method for forming a FET device
- Patent number 12,324,175
- Issue date Jun 3, 2025
- Imec VZW
- Julien Ryckaert
Information Patent Grant
Method for forming a buried metal line in a semiconductor substrate
- Patent number 12,237,207
- Issue date Feb 25, 2025
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device
- Patent number 12,237,371
- Issue date Feb 25, 2025
- IMEC VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device and a semiconductor device
- Patent number 12,154,832
- Issue date Nov 26, 2024
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact isolation in semiconductor devices
- Patent number 11,862,452
- Issue date Jan 2, 2024
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate spacer patterning
- Patent number 11,854,803
- Issue date Dec 26, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for filling a space in a semiconductor
- Patent number 11,824,122
- Issue date Nov 21, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming transistor structures
- Patent number 11,682,591
- Issue date Jun 20, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for processing a semiconductor device with two closely space...
- Patent number 11,638,391
- Issue date Apr 25, 2023
- Imec VZW
- Boon Teik Chan
Information Patent Grant
Method for processing a FinFET device
- Patent number 11,610,980
- Issue date Mar 21, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated semiconductor layer stacks for a semiconductor device
- Patent number 11,545,401
- Issue date Jan 3, 2023
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of semiconductor device processing
- Patent number 11,527,431
- Issue date Dec 13, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned layer patterning
- Patent number 11,488,826
- Issue date Nov 1, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing self-aligned gate and source/drain via connect...
- Patent number 11,430,876
- Issue date Aug 30, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a mask layer
- Patent number 11,430,697
- Issue date Aug 30, 2022
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split replacement metal gate integration
- Patent number 11,348,842
- Issue date May 31, 2022
- Imec VZW
- Eugenio Dentoni Litta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a buried metal line
- Patent number 11,335,597
- Issue date May 17, 2022
- Imec VZW
- Eugenio Dentoni Litta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating stacked semiconductor device
- Patent number 11,107,812
- Issue date Aug 31, 2021
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Removing an organic sacrificial material from a two-dimensional mat...
- Patent number 11,056,376
- Issue date Jul 6, 2021
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a gate cut structure on an array of semiconduc...
- Patent number 10,978,335
- Issue date Apr 13, 2021
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a pillar structure in a semiconductor layer
- Patent number 10,825,682
- Issue date Nov 3, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for forming horizontal nanowires and devices manufactured th...
- Patent number 10,790,382
- Issue date Sep 29, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Reticles for lithography
- Patent number 10,782,607
- Issue date Sep 22, 2020
- Imec VZW
- Boon Teik Chan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Area-selective deposition of a tantalum silicide TaSix mask material
- Patent number 10,784,158
- Issue date Sep 22, 2020
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming micro-pipes on a substrate and a structure formed...
- Patent number 10,493,378
- Issue date Dec 3, 2019
- Imec VZW
- Zheng Tao
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method for blocking a trench portion
- Patent number 10,490,442
- Issue date Nov 26, 2019
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal of ceramic material hardened pattern
- Patent number 10,303,048
- Issue date May 28, 2019
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing fin structures of a semiconductor device in a...
- Patent number 10,192,956
- Issue date Jan 29, 2019
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming internal spacer for nanowires
- Patent number 10,153,341
- Issue date Dec 11, 2018
- Imec VZW
- Zheng Tao
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Self-aligned nanostructures for semiconductor devices
- Patent number 10,128,371
- Issue date Nov 13, 2018
- Imec VZW
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
- Publication number 20250212495
- Publication date Jun 26, 2025
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Semiconductor Structure
- Publication number 20250212494
- Publication date Jun 26, 2025
- IMEC vzw
- Serge Biesemans
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Processing a CFET Device with Non-conformal Gate Dielectric
- Publication number 20250133815
- Publication date Apr 24, 2025
- IMEC vzw
- Antony Premkumar PETER
Information Patent Application
COMPLEMENTARY FIELD EFFECT TRANSISTOR DEVICES AND METHODS OF PROCES...
- Publication number 20250113601
- Publication date Apr 3, 2025
- IMEC vzw
- Boon Teik Chan
Information Patent Application
Method for Forming a Self-aligned Buried Power Rail in a Nanosheet-...
- Publication number 20250107199
- Publication date Mar 27, 2025
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and a Method for Forming a Semiconductor Device
- Publication number 20250087643
- Publication date Mar 13, 2025
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE AND LOW POWER THREE-DIMENSIONAL STATIC RANDOM ACCE...
- Publication number 20240373617
- Publication date Nov 7, 2024
- IMEC vzw
- Hsiao-Hsuan Liu
Information Patent Application
INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WIT...
- Publication number 20240290660
- Publication date Aug 29, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...
- Publication number 20240234207
- Publication date Jul 11, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Devices and Methods for Making Such Devices
- Publication number 20240213312
- Publication date Jun 27, 2024
- IMEC vzw
- Gaspard Hiblot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR DEVICE
- Publication number 20240204080
- Publication date Jun 20, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR DEVICE
- Publication number 20240204081
- Publication date Jun 20, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Semiconductor Device
- Publication number 20240204082
- Publication date Jun 20, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked SRAM Cell with a Dual-Side Interconnect Structure
- Publication number 20240206145
- Publication date Jun 20, 2024
- IMEC vzw
- Hsiao-Hsuan Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR DEVICE
- Publication number 20240154006
- Publication date May 9, 2024
- IMEC vzw
- Zheng Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...
- Publication number 20240136225
- Publication date Apr 25, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20240006228
- Publication date Jan 4, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bit Cell for Static Random Access Memory
- Publication number 20230413504
- Publication date Dec 21, 2023
- IMEC vzw
- Hsiao-Hsuan Liu
Information Patent Application
Bit Cell with Isolating Wall
- Publication number 20230413505
- Publication date Dec 21, 2023
- IMEC vzw
- Hsiao-Hsuan Liu
Information Patent Application
Method for Forming a Stacked Transistor Device
- Publication number 20230386928
- Publication date Nov 30, 2023
- IMEC vzw
- Boon Teik CHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit cell for a standard cell semiconductor device
- Publication number 20230361205
- Publication date Nov 9, 2023
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA FORMATION IN AN INTEGRATED CIRCUIT
- Publication number 20230197528
- Publication date Jun 22, 2023
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Stacked FET Device
- Publication number 20230197830
- Publication date Jun 22, 2023
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Semiconductor Device
- Publication number 20230197831
- Publication date Jun 22, 2023
- IMEC vzw
- Boon Teik CHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Semiconductor Device
- Publication number 20230197522
- Publication date Jun 22, 2023
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Semiconductor Device Structure
- Publication number 20230197525
- Publication date Jun 22, 2023
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FET DEVICE
- Publication number 20230178635
- Publication date Jun 8, 2023
- IMEC vzw
- Aryan Afzalian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FET DEVICE
- Publication number 20230178630
- Publication date Jun 8, 2023
- IMEC vzw
- Boon Teik CHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A FET DEVICE
- Publication number 20230178629
- Publication date Jun 8, 2023
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FET DEVICE AND A METHOD FOR FORMING A FET DEVICE
- Publication number 20220199809
- Publication date Jun 23, 2022
- IMEC vzw
- Julien RYCKAERT
- H01 - BASIC ELECTRIC ELEMENTS

Boon Teik Chan

Person

Patents Grantslast 30 patents

FET device and a method for forming a FET device

Method for forming a buried metal line in a semiconductor substrate

Method for forming a semiconductor device

Method for forming a semiconductor device and a semiconductor device

Contact isolation in semiconductor devices

Gate spacer patterning

Method for filling a space in a semiconductor

Method for forming transistor structures

Method for processing a semiconductor device with two closely space...

Method for processing a FinFET device

Isolated semiconductor layer stacks for a semiconductor device

Methods of semiconductor device processing

Self-aligned layer patterning

Method for producing self-aligned gate and source/drain via connect...

Method of forming a mask layer

Split replacement metal gate integration

Method for forming a buried metal line

Method of fabricating stacked semiconductor device

Removing an organic sacrificial material from a two-dimensional mat...

Method for producing a gate cut structure on an array of semiconduc...

Method for producing a pillar structure in a semiconductor layer

Method for forming horizontal nanowires and devices manufactured th...

Reticles for lithography

Area-selective deposition of a tantalum silicide TaSix mask material

Method of forming micro-pipes on a substrate and a structure formed...

Method for blocking a trench portion

Metal of ceramic material hardened pattern

Method for producing fin structures of a semiconductor device in a...

Method of forming internal spacer for nanowires

Self-aligned nanostructures for semiconductor devices

Patents Applicationslast 30 patents

METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE

Method for Forming a Semiconductor Structure

Method for Processing a CFET Device with Non-conformal Gate Dielectric

COMPLEMENTARY FIELD EFFECT TRANSISTOR DEVICES AND METHODS OF PROCES...

Method for Forming a Self-aligned Buried Power Rail in a Nanosheet-...

Semiconductor Device and a Method for Forming a Semiconductor Device

HIGH PERFORMANCE AND LOW POWER THREE-DIMENSIONAL STATIC RANDOM ACCE...

INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WIT...

METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...

Integrated Circuit Devices and Methods for Making Such Devices

METHOD FOR FORMING A SEMICONDUCTOR DEVICE

METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Method for Forming a Semiconductor Device

Stacked SRAM Cell with a Dual-Side Interconnect Structure

METHOD FOR FORMING A SEMICONDUCTOR DEVICE

METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...

Method for Forming a Buried Metal Line in a Semiconductor Substrate

Bit Cell for Static Random Access Memory

Bit Cell with Isolating Wall

Method for Forming a Stacked Transistor Device

Circuit cell for a standard cell semiconductor device

VIA FORMATION IN AN INTEGRATED CIRCUIT

Method for Forming a Stacked FET Device

Method for Forming a Semiconductor Device

Method for Forming a Semiconductor Device

Method for Forming a Semiconductor Device Structure

METHOD FOR FORMING A FET DEVICE

METHOD FOR FORMING A FET DEVICE

METHOD FOR FORMING A FET DEVICE

FET DEVICE AND A METHOD FOR FORMING A FET DEVICE