Boyd L. Coomer

Person

Scottsdale, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for manufacturing imprinted substrates
- Patent number 7,637,008
- Issue date Dec 29, 2009
- Intel Corporation
- Thomas S. Dory
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate conductive post formation
- Patent number 7,358,116
- Issue date Apr 15, 2008
- Intel Corporation
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layer integrated circuit package
- Patent number 7,245,001
- Issue date Jul 17, 2007
- Intel Corporation
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for making an imprinted conductive circuit usi...
- Patent number 6,974,775
- Issue date Dec 13, 2005
- Intel Corporation
- Milan Keser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer integrated circuit package
- Patent number 6,899,815
- Issue date May 31, 2005
- Intel Corporation
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and system to manufacture stacked chip devices
- Patent number 6,777,648
- Issue date Aug 17, 2004
- Intel Corporation
- Boyd L. Coomer
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Dielectric with fluorescent material
- Publication number 20050123860
- Publication date Jun 9, 2005
- Paul Koning
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-layer integrated circuit package
- Publication number 20050009353
- Publication date Jan 13, 2005
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and system to manufacture stacked chip devices
- Publication number 20040222512
- Publication date Nov 11, 2004
- Intel Corporation
- Boyd L. Coomer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of semi-additive plating of imprinted layers and resulting p...
- Publication number 20040124533
- Publication date Jul 1, 2004
- Milan Keser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for performing substrate imprinting using thermoset resin v...
- Publication number 20040126547
- Publication date Jul 1, 2004
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Imprinted substrate and methods of manufacture
- Publication number 20040118594
- Publication date Jun 24, 2004
- Intel Corporation
- Thomas S. Dory
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Substrate conductive post formation
- Publication number 20030203623
- Publication date Oct 30, 2003
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-layer integrated circuit package
- Publication number 20030184987
- Publication date Oct 2, 2003
- Boyd L. Coomer
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and system to manufacture stacked chip devices
- Publication number 20030132527
- Publication date Jul 17, 2003
- Boyd L. Coomer
- H01 - BASIC ELECTRIC ELEMENTS

Boyd L. Coomer

Person

Patents Grantslast 30 patents

Methods for manufacturing imprinted substrates

Substrate conductive post formation

Multi-layer integrated circuit package

Method and apparatus for making an imprinted conductive circuit usi...

Multi-layer integrated circuit package

Method and system to manufacture stacked chip devices

Patents Applicationslast 30 patents

Dielectric with fluorescent material

Multi-layer integrated circuit package

Method and system to manufacture stacked chip devices

Method of semi-additive plating of imprinted layers and resulting p...

Methods for performing substrate imprinting using thermoset resin v...

Imprinted substrate and methods of manufacture

Substrate conductive post formation

Multi-layer integrated circuit package

Method and system to manufacture stacked chip devices