Bradley A. Sharpe-Geisler

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive power-on-reset generator systems and methods for programma...
- Patent number 11,907,033
- Issue date Feb 20, 2024
- Lattice Semiconductor Corporation
- Chwei-Po Chew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-speed bus triggering methods and circuitry
- Patent number 10,884,452
- Issue date Jan 5, 2021
- LATTICE SEMICONDUCTOR CORPORATION
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Acoustic gesture recognition systems and methods
- Patent number 10,764,026
- Issue date Sep 1, 2020
- Lattice Semiconductor Corporation
- Bradley Sharpe-Geisler
- G01 - MEASURING TESTING
Information Patent Grant
Low-speed bus time stamp methods and circuitry
- Patent number 10,466,738
- Issue date Nov 5, 2019
- LATTICE SEMICONDUCTOR CORPORATION
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock recovery and data recovery for programmable logic devices
- Patent number 10,326,627
- Issue date Jun 18, 2019
- LATTICE SEMICONDUCTOR CORPORATION
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock recovery and data recovery for programmable logic devices
- Patent number 10,148,472
- Issue date Dec 4, 2018
- LATTICE SEMICONDUCTOR CORPORATION
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA integrated circuit having embedded sram memory blocks with reg...
- Patent number RE39510
- Issue date Mar 13, 2007
- Lattice Semiconductor Corporation
- Om P. Agrawal
- 326 - Electronic digital logic circuitry
Information Patent Grant
FPGA with register-intensive architecture
- Patent number 7,028,281
- Issue date Apr 11, 2006
- Lattice Semiconductor Corporation
- Om P Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical general interconnect architecture for high density FPGA'S
- Patent number 7,000,212
- Issue date Feb 14, 2006
- Lattice Semiconductor Corporation
- Om P Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array having embedded memory with configura...
- Patent number 6,919,736
- Issue date Jul 19, 2005
- Lattice Semiconductor Corporation
- Om P. Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input buffer with CMOS driver gate current control enabling selecta...
- Patent number 6,870,391
- Issue date Mar 22, 2005
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer with overvoltage protection
- Patent number 6,798,244
- Issue date Sep 28, 2004
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge protection circuit
- Patent number 6,760,209
- Issue date Jul 6, 2004
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable optimized-distribution logic allocator for a high-dens...
- Patent number 6,753,696
- Issue date Jun 22, 2004
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalable and parallel processing methods and structures for testing...
- Patent number 6,725,442
- Issue date Apr 20, 2004
- Lattice Semiconductor Corporation
- Richard T. Cote
- G01 - MEASURING TESTING
Information Patent Grant
Band gap reference circuit
- Patent number 6,720,755
- Issue date Apr 13, 2004
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- G05 - CONTROLLING REGULATING
Information Patent Grant
Input buffer with voltage clamping for compatibility
- Patent number 6,714,048
- Issue date Mar 30, 2004
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer having programmable drive current and output voltage...
- Patent number 6,714,043
- Issue date Mar 30, 2004
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer with feedback from an input buffer to provide selecta...
- Patent number 6,657,458
- Issue date Dec 2, 2003
- Lattice Semiconductor Corporation
- Bradley A. Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable grain architecture for FPGA integrated circuits
- Patent number 6,621,298
- Issue date Sep 16, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for configuring FPGA's having variable grain compon...
- Patent number 6,590,415
- Issue date Jul 8, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable optimized-distribution logic allocator for a high-dens...
- Patent number 6,531,890
- Issue date Mar 11, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for configuring FPGA's having variable grain blocks...
- Patent number 6,526,558
- Issue date Feb 25, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalable and parallel processing methods and structures for testing...
- Patent number 6,470,485
- Issue date Oct 22, 2002
- Lattice Semiconductor Corporation
- Richard T. Cote
- G01 - MEASURING TESTING
Information Patent Grant
Variable grain architecture for FPGA integrated circuits
- Patent number 6,380,759
- Issue date Apr 30, 2002
- Vantis Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuitry to provide fast carry
- Patent number 6,359,466
- Issue date Mar 19, 2002
- Vantis Corporation
- Bradley A. Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree topology
- Patent number 6,353,352
- Issue date Mar 5, 2002
- Vantis Corporation
- Bradley A. Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output buffer for making a high voltage (5.0 volt) compatible input...
- Patent number 6,351,157
- Issue date Feb 26, 2002
- Vantis Corporation
- Bradley A. Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Inversion of product term line before or logic in a programmable lo...
- Patent number 6,326,808
- Issue date Dec 4, 2001
- Vantis Corporation
- Mathew Fisk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for configuring FPGA's having variable grain blocks...
- Patent number 6,292,930
- Issue date Sep 18, 2001
- Vantis Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DUAL POWER SUPPLIED MEMORY CELLS AND DETERMINISTIC RESET THEREOF FO...
- Publication number 20240185908
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Loren L. McLaury
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Insertion Delay Systems and Methods
- Publication number 20240183902
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVELY POWERED EMBEDDED MEMORY SYSTEMS AND METHODS
- Publication number 20240184459
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE POWER-ON-RESET GENERATOR SYSTEMS AND METHODS FOR PROGRAMMA...
- Publication number 20220291731
- Publication date Sep 15, 2022
- Lattice Semiconductor Corporation
- Chwei-Po Chew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-SPEED BUS TIME STAMP METHODS AND CIRCUITRY
- Publication number 20200019209
- Publication date Jan 16, 2020
- Lattice Semiconductor Corporation
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-SPEED BUS TIME STAMP METHODS AND CIRCUITRY
- Publication number 20180196465
- Publication date Jul 12, 2018
- Bradley SHARPE-GEISLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20180069736
- Publication date Mar 8, 2018
- Lattice Semiconductor Corporation
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20180069735
- Publication date Mar 8, 2018
- Lattice Semiconductor Corporation
- Bradley Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACOUSTIC GESTURE RECOGNITION SYSTEMS AND METHODS
- Publication number 20170041127
- Publication date Feb 9, 2017
- Lattice Semiconductor Corporation
- Bradley Sharpe-Geisler
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical general interconnect architecture for high density fpga's
- Publication number 20040010767
- Publication date Jan 15, 2004
- Lattice Semiconductor Corporation
- Om P. Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for configuring FPGA ' S having viriable grain components f...
- Publication number 20020196809
- Publication date Dec 26, 2002
- Vantis Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Variable grain architecture for FPGA integrated circuits
- Publication number 20020186044
- Publication date Dec 12, 2002
- Vantis Corporation
- Om P. Agrawal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for configuring FPGA's having variable grain blocks and sha...
- Publication number 20010056570
- Publication date Dec 27, 2001
- Vantis Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor - oxide - semiconductor capacitor formed in intergtat...
- Publication number 20010015449
- Publication date Aug 23, 2001
- Vantis Corporation
- Bai Niguyen
- H01 - BASIC ELECTRIC ELEMENTS

Bradley A. Sharpe-Geisler

Person

Patents Grantslast 30 patents

Adaptive power-on-reset generator systems and methods for programma...

Low-speed bus triggering methods and circuitry

Acoustic gesture recognition systems and methods

Low-speed bus time stamp methods and circuitry

Clock recovery and data recovery for programmable logic devices

Clock recovery and data recovery for programmable logic devices

FPGA integrated circuit having embedded sram memory blocks with reg...

FPGA with register-intensive architecture

Hierarchical general interconnect architecture for high density FPGA'S

Field programmable gate array having embedded memory with configura...

Input buffer with CMOS driver gate current control enabling selecta...

Output buffer with overvoltage protection

Electrostatic discharge protection circuit

Programmable optimized-distribution logic allocator for a high-dens...

Scalable and parallel processing methods and structures for testing...

Band gap reference circuit

Input buffer with voltage clamping for compatibility

Output buffer having programmable drive current and output voltage...

Output buffer with feedback from an input buffer to provide selecta...

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA&#x00027;s having variable grain compon...

Programmable optimized-distribution logic allocator for a high-dens...

Methods for configuring FPGA&#x00027;s having variable grain blocks...

Scalable and parallel processing methods and structures for testing...

Variable grain architecture for FPGA integrated circuits

Circuitry to provide fast carry

Clock tree topology

Output buffer for making a high voltage (5.0 volt) compatible input...

Inversion of product term line before or logic in a programmable lo...

Methods for configuring FPGA&#x00027;s having variable grain blocks...

Patents Applicationslast 30 patents

DUAL POWER SUPPLIED MEMORY CELLS AND DETERMINISTIC RESET THEREOF FO...

Clock Insertion Delay Systems and Methods

SELECTIVELY POWERED EMBEDDED MEMORY SYSTEMS AND METHODS

ADAPTIVE POWER-ON-RESET GENERATOR SYSTEMS AND METHODS FOR PROGRAMMA...

LOW-SPEED BUS TIME STAMP METHODS AND CIRCUITRY

LOW-SPEED BUS TIME STAMP METHODS AND CIRCUITRY

CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES

CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES

ACOUSTIC GESTURE RECOGNITION SYSTEMS AND METHODS

Hierarchical general interconnect architecture for high density fpga's

Methods for configuring FPGA ' S having viriable grain components f...

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA's having variable grain blocks and sha...

Semiconductor - oxide - semiconductor capacitor formed in intergtat...

Methods for configuring FPGA's having variable grain compon...

Methods for configuring FPGA's having variable grain blocks...

Methods for configuring FPGA's having variable grain blocks...