Brian C. Gaide

Person

Erie, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Yield recovery scheme for memory
- Patent number 12,154,617
- Issue date Nov 26, 2024
- Xilinx, Inc.
- Brian C. Gaide
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for secure deconstruction sensor in a heterogeneo...
- Patent number 12,093,394
- Issue date Sep 17, 2024
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming and/or configuring stacked dies
- Patent number 11,961,823
- Issue date Apr 16, 2024
- Xilinx, Inc.
- Praful Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Universal interposer for a semiconductor package
- Patent number 11,901,300
- Issue date Feb 13, 2024
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock tree routing in a chip stack
- Patent number 11,868,174
- Issue date Jan 9, 2024
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute dataflow architecture
- Patent number 11,750,195
- Issue date Sep 5, 2023
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive integrated programmable device platform
- Patent number 11,683,038
- Issue date Jun 20, 2023
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compute dataflow architecture
- Patent number 11,451,230
- Issue date Sep 20, 2022
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power delivery network for active-on-active stacked integrated circ...
- Patent number 11,270,977
- Issue date Mar 8, 2022
- Xilinx, Inc.
- Praful Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip stacked devices
- Patent number 11,239,203
- Issue date Feb 1, 2022
- Xilinx, Inc.
- Brian C. Gaide
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive integrated programmable device platform
- Patent number 11,063,594
- Issue date Jul 13, 2021
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Forming and/or configuring stacked dies
- Patent number 11,043,480
- Issue date Jun 22, 2021
- Xilinx, Inc.
- Praful Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Yield-centric power gated regulated supply design with programmable...
- Patent number 11,017,822
- Issue date May 25, 2021
- Xilinx, Inc.
- Sree Rkc Saraswatula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable termination circuits for programmable devices
- Patent number 10,998,904
- Issue date May 4, 2021
- Xilinx, Inc.
- Sundeep Ram Gopal Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Global clock and a leaf clock divider
- Patent number 10,871,796
- Issue date Dec 22, 2020
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundancy scheme for multi-chip stacked devices
- Patent number 10,825,772
- Issue date Nov 3, 2020
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redundancy scheme for a 3D stacked device
- Patent number 10,741,524
- Issue date Aug 11, 2020
- Xilinx, Inc.
- Brian C. Gaide
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Configurable logic block (CLB) internal routing architecture for en...
- Patent number 10,715,149
- Issue date Jul 14, 2020
- Xilinx, Inc.
- Eric F. Dellinger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive integrated programmable device platform
- Patent number 10,673,439
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable pipeline interface circuit
- Patent number 10,320,386
- Issue date Jun 11, 2019
- Xilinx, Inc.
- Ilya K. Ganusov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selectively providing clock signals using a programmable control ci...
- Patent number 10,284,185
- Issue date May 7, 2019
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed voltage and temperature compensation for clock deskewing
- Patent number 10,110,202
- Issue date Oct 23, 2018
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Using an integrated circuit die for multiple devices
- Patent number 10,043,724
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Brian C. Gaide
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed multi-die routing in a multi-chip module
- Patent number 9,859,896
- Issue date Jan 2, 2018
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Lut cascading circuit
- Patent number 9,602,108
- Issue date Mar 21, 2017
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits for and methods of generating clock signals enabling the l...
- Patent number 9,559,669
- Issue date Jan 31, 2017
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interconnect multiplexers and methods of reducing contention curren...
- Patent number 9,509,307
- Issue date Nov 29, 2016
- Xilinx, Inc.
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable power reduction technique using transistor threshold d...
- Patent number 9,496,871
- Issue date Nov 15, 2016
- Xilinx, Inc.
- Benjamin S. Devlin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascaded LUT carry logic circuit
- Patent number 9,455,714
- Issue date Sep 27, 2016
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits for and methods of controlling power within an integrated...
- Patent number 9,438,244
- Issue date Sep 6, 2016
- Xilinx, Inc.
- Santosh Kumar Sood
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY
- Publication number 20250004983
- Publication date Jan 2, 2025
- Xilinx, Inc.
- Brian C. GAIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS TO EXTEND NOC INTERCONNECT ACROSS MULTIPLE DICE IN 3D
- Publication number 20240403253
- Publication date Dec 5, 2024
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDING SOFT LOGIC TO FLUSH A PIPELINE AND REDUCE CURRENT RAMP
- Publication number 20240385642
- Publication date Nov 21, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BANDWIDTH THROUGH VERTICAL CONNECTIONS
- Publication number 20240387388
- Publication date Nov 21, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUNDANCY SCHEME FOR ACTIVATING CIRCUITRY ON A BASE DIE OF A 3D st...
- Publication number 20240330222
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT
- Publication number 20240313781
- Publication date Sep 19, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SECURE DECONSTRUCTION SENSOR IN A HETEROGENEO...
- Publication number 20240281537
- Publication date Aug 22, 2024
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP PACKAGE INTEGRATION WITH HYBRID BONDED BRIDGE DIE
- Publication number 20240203968
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Jaspreet Singh GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
U-TURN CIRCUITRY TO CONVERT INTER-LAYER CONNECTIONS OF AN INTEGRATE...
- Publication number 20240194645
- Publication date Jun 13, 2024
- Xilinx, Inc.
- Jay T. YOUNG
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK TREE ROUTING IN A CHIP STACK
- Publication number 20240103562
- Publication date Mar 28, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
YIELD RECOVERY SCHEME FOR MEMORY
- Publication number 20240096405
- Publication date Mar 21, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM
- Publication number 20230291405
- Publication date Sep 14, 2023
- Xilinx, Inc.
- Sagheer Ahmad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
UNIVERSAL INTERPOSER FOR A SEMICONDUCTOR PACKAGE
- Publication number 20230268280
- Publication date Aug 24, 2023
- Xilinx, Inc.
- Jaspreet Singh GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPUTE DATAFLOW ARCHITECTURE
- Publication number 20220368330
- Publication date Nov 17, 2022
- Xilinx, Inc.
- Steven P. YOUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK TREE ROUTING IN A CHIP STACK
- Publication number 20220197329
- Publication date Jun 23, 2022
- Xilinx, Inc.
- Brian C. GAIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE DATAFLOW ARCHITECTURE
- Publication number 20210336622
- Publication date Oct 28, 2021
- Xilinx, Inc.
- Steven P. YOUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER DELIVERY NETWORK FOR ACTIVE-ON-ACTIVE STACKED INTEGRATED CIRC...
- Publication number 20210143127
- Publication date May 13, 2021
- Xilinx, Inc.
- Praful JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP STACKED DEVICES
- Publication number 20210134760
- Publication date May 6, 2021
- Xilinx, Inc.
- Brian C. GAIDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUNDANCY SCHEME FOR MULTI-CHIP STACKED DEVICES
- Publication number 20200303311
- Publication date Sep 24, 2020
- Xilinx, Inc.
- Steven P. YOUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUNDANCY SCHEME FOR A 3D STACKED DEVICE
- Publication number 20190333892
- Publication date Oct 31, 2019
- Xilinx, Inc.
- Brian C. Gaide
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE PIPELINE INTERFACE CIRCUIT
- Publication number 20190181863
- Publication date Jun 13, 2019
- Xilinx, Inc.
- Ilya K. Ganusov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED...
- Publication number 20160118988
- Publication date Apr 28, 2016
- Xilinx, Inc.
- Santosh Kumar Sood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK NETWORK ARCHITECTURE
- Publication number 20140132305
- Publication date May 15, 2014
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20120019292
- Publication date Jan 26, 2012
- Xilinx, Inc.
- Weiguang Lu
- G06 - COMPUTING CALCULATING COUNTING

Brian C. Gaide

Person

Patents Grantslast 30 patents

Yield recovery scheme for memory

System and method for secure deconstruction sensor in a heterogeneo...

Forming and/or configuring stacked dies

Universal interposer for a semiconductor package

Clock tree routing in a chip stack

Compute dataflow architecture

Adaptive integrated programmable device platform

Compute dataflow architecture

Power delivery network for active-on-active stacked integrated circ...

Multi-chip stacked devices

Adaptive integrated programmable device platform

Forming and/or configuring stacked dies

Yield-centric power gated regulated supply design with programmable...

Programmable termination circuits for programmable devices

Global clock and a leaf clock divider

Redundancy scheme for multi-chip stacked devices

Redundancy scheme for a 3D stacked device

Configurable logic block (CLB) internal routing architecture for en...

Adaptive integrated programmable device platform

Programmable pipeline interface circuit

Selectively providing clock signals using a programmable control ci...

Distributed voltage and temperature compensation for clock deskewing

Using an integrated circuit die for multiple devices

Distributed multi-die routing in a multi-chip module

Lut cascading circuit

Circuits for and methods of generating clock signals enabling the l...

Interconnect multiplexers and methods of reducing contention curren...

Programmable power reduction technique using transistor threshold d...

Cascaded LUT carry logic circuit

Circuits for and methods of controlling power within an integrated...

Patents Applicationslast 30 patents

TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY

METHODS TO EXTEND NOC INTERCONNECT ACROSS MULTIPLE DICE IN 3D

ADDING SOFT LOGIC TO FLUSH A PIPELINE AND REDUCE CURRENT RAMP

MEMORY BANDWIDTH THROUGH VERTICAL CONNECTIONS

REDUNDANCY SCHEME FOR ACTIVATING CIRCUITRY ON A BASE DIE OF A 3D st...

PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT

SYSTEM AND METHOD FOR SECURE DECONSTRUCTION SENSOR IN A HETEROGENEO...

CHIP PACKAGE INTEGRATION WITH HYBRID BONDED BRIDGE DIE

U-TURN CIRCUITRY TO CONVERT INTER-LAYER CONNECTIONS OF AN INTEGRATE...

CLOCK TREE ROUTING IN A CHIP STACK

YIELD RECOVERY SCHEME FOR MEMORY

ADAPTIVE INTEGRATED PROGRAMMABLE DEVICE PLATFORM

UNIVERSAL INTERPOSER FOR A SEMICONDUCTOR PACKAGE

COMPUTE DATAFLOW ARCHITECTURE

CLOCK TREE ROUTING IN A CHIP STACK

COMPUTE DATAFLOW ARCHITECTURE

POWER DELIVERY NETWORK FOR ACTIVE-ON-ACTIVE STACKED INTEGRATED CIRC...

MULTI-CHIP STACKED DEVICES

REDUNDANCY SCHEME FOR MULTI-CHIP STACKED DEVICES

REDUNDANCY SCHEME FOR A 3D STACKED DEVICE

PROGRAMMABLE PIPELINE INTERFACE CIRCUIT

CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED...

CLOCK NETWORK ARCHITECTURE

CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT