Patent Application
20240194645
Examples of the present disclosure generally relate to circuitry to convert interlayer connections of an integrated circuit device to intra-layer connections.
An integrated circuit (IC) device may include vertically stacked IC chips, where each IC chip includes functional circuitry and inter-layer connection circuitry to provide vertical connections between adjacent IC chips. In some situations, the inter-layer connection circuitry may be unused or underutilized.
Circuitry to convert inter-layer connections of an integrated circuit device to intra-layer connections are described. One example described herein is an integrated circuit (IC) device that includes a block of integrated circuitry that includes functional circuitry and configurable interface circuitry, where the configurable interface circuitry includes output circuitry that route a node of the functional circuitry to an output node of the block and input circuitry that routes a selectable one of the output node of the block and an input node of the first block to the functional circuitry.
Another example described herein is an IC device that includes a stack of multiple blocks of integrated circuitry, wherein a first one of the blocks comprises functional circuitry and configurable interface circuitry, where the configurable interface circuitry routes a first node of the functional circuitry to an output node of the first block and routes a selectable one of the output node of the first block and an input node of the first block to a second node of the functional circuitry, where the output node and the input node of the first block are coupled to respective input and output nodes of an adjacent one of the blocks.
Another example described herein is an IC device that includes a stack of multiple blocks of integrated circuitry, where each block includes functional circuitry and configurable interface circuitry, and where the configurable interface circuitry includes output circuitry that routes n output nodes of the functional circuitry to n respective output nodes of the block, and n blocks of input multiplexer circuitry, each including a first input coupled to a respective one of n output nodes of the block, a second input coupled to a respective one of the n input nodes of the block, and an output coupled to a respect one of n input nodes of the functional circuitry.
So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples.
Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the features or as a limitation on the scope of the claims. In addition, an illustrated example need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated, or if not so explicitly described.
An integrated circuit (IC) chip designed for a 3-dimensional (3D) or stacked IC device may include inter-layer connection circuitry (e.g., vertical connections and supporting multiplexers) to connect neighboring or adjacent chip layers on either side of the IC chip. In some situations, the inter-layer connection circuitry is unused or underutilized. For example, if the IC chip is the upper-most IC chip in a stack (i.e., where there is no connectivity above the IC chip), or if the IC chip is the lowest chip in a stack (i.e., where there is sparse connectivity with a base layer), half of the inter-layer connection circuitry may go unused. As another example, if the IC chip is used in a 2-dimensional scenario, all of the inter-layer connection circuitry may be unused.
Embodiments herein describe techniques to repurpose inter-layer connection circuitry to provide intra-layer connections (i.e., connections within functional circuitry or within a fabric of an IC chip).
Embodiments herein include configurable circuitry that selectively reroutes an output of inter-layer connection circuitry back to the functional circuitry or fabric of an IC chip. The configurable circuitry may be referred to as U-turn or loop-back circuitry. The configurable circuitry may include a 2-input multiplexer for each inter-layer output. The configurable circuitry may utilize relatively little area and may consume relatively little additional power, with relatively little delay.
Embodiments herein may be useful to convert inter-layer connection circuitry to intra-layer connection circuitry, such as when an IC chip is used in a 2D application. Embodiments herein may also be useful to use inter-layer connection circuitry for both inter-layer connections and intra-layer connections (i.e., when the IC chip is used in a 3D or stacked application). In other words, embodiments herein may be useful when an IC chip is used in 3D stack or a 2D application.
Embodiments herein may be useful to improve design routability and/or performance of an IC chip. Results on a fabricated design suite designed specifically for fabric routability testing by increasing connectivity and logic utilization showed an increase in designs routed of between 10% and 20% where the baseline is designed to route approximately 50% of the designs. For example the baseline architecture routed 50 of 100 designs and the addition described here routed improved to ˜60 of 100 designs attempted.
Blocks 102-1 through 102-n may be collectively referred to as blocks 102. Functional circuitry 104-1 through 104-n may be collectively referred to as functional circuitry 104. Configurable interface circuitry 106-1 through 106-n may be collectively referred to as configurable interface circuitry 106. Configurable interface circuitry 108-1 through 108-n may be collectively referred to as configurable interface circuitry 108.
Functional circuitry 104-1 through 104-n may include, without limitation, fixed function circuitry/logic, configurable/programmable circuitry/logic, processor circuitry, memory, and/or combinations thereof. Functional circuitry 104-1 through 104-n, or a subset thereof may differ from one another (i.e., heterogeneous functional circuitry). Alternatively, functional circuitry 104-1 through 104-n, or a subset thereof may be similar or identical to one another (i.e., homogeneous functional circuitry).
Blocks 102 may include external nodes (e.g., input and/or output nodes) exposed through surfaces thereof, such as described below with reference to
Node 202-1 may represent an output node of block 102-1, and node 208-2 may represent a corresponding input node of block 102-2. Node 204-1 may represent an input node of block 102-1, and node 210-2 may represent a corresponding output node of block 102-2. Nodes 202-1, 204-1, 208-2, and 210-2 may be positioned on respective surfaces 206-1 and 212-2 such that nodes 202-1 and 204-1 physically align with nodes 208-2 and 210-2 when block 102-2 is positioned or stacked on block 102-1. Blocks 102-1 and 102-2 may include additional input and/or output nodes.
Configurable interface circuitry 106 and configurable interface circuitry 108 interface between functional circuitry 104 of adjacent blocks 102. For example, configurable interface circuitry 108-1 couples nodes of functional circuitry 104-1 to nodes 202-1 and 204-1, and configurable interface circuitry 106-2 couples nodes of functional circuitry 104-2 to nodes 208-2 and 210-2.
Configurable interface circuitry 106-1 through 106-n and 108-1 through 108-n may be identical to one another, which may be useful to provide blocks 102 with standardized configurable interfaces to adjacent layers.
In the examples of
In an embodiment, configurable interface circuitry 106 and configurable interface circuitry 108 include configurable loop-back or U-turn circuitry to selectively route an output node back to the respective functional circuitry 104.
Configurable interface circuitry 108-1 further includes input circuitry 308 that couples a selectable one of input node 204-1 and output node 202-1 (i.e., output 312 of output circuitry 302) to an input node 310 of functional circuitry 104-1. In other words, output 312 may be looped back or returned to functional circuitry 104-1.
Looping back or returning output 312 to functional circuitry 104-1 may be referred to as a U-turn, which may be useful in one or more of a variety of situations or applications. For example, in
Further in the example of
Configurable interface circuitry 106-2 further includes input circuitry 326 that couples a selectable one of input node 208-2 and output node 210-2 (I.e., output 328 of output circuitry 320) to an input node 330 of functional circuitry 104-2. In other words, output 328 may be looped back or returned to functional circuitry 104-2, such as described above with respect to output 312 of configurable interface circuitry 108-1.
In the example of
Output circuitry 302 and 320 may include n:m multiplexer circuitry that receives m inputs from respective functional circuitry 104 and provides a selectable subset of n of the m inputs to n respective output nodes, where m and n are positive integers, and m is greater than n. In the example of
Configurable interface circuitry 106 and/or 108 may be one-time or permanently configurable (e.g., factory-configured via E-fuses), or may be reconfigurable (e.g., at power-up/boot or dynamically during operation). In
Configuration registers may include volatile and/or non-volatile storage circuitry. Non-volatile configuration registers may be useful to retain configuration parameters when power is removed from IC device 100. Volatile configuration registers may be useful to program configurable interface circuitry when IC device is powered up and/or to dynamically reprogram the configurable interface circuitry.
In the example of
Output circuitry 402 includes a first set of multiplexer circuits 410-1 through 410-4, illustrated here as 8:1 multiplexer circuits that receive respective inputs 404-1 through 404-4. Outputs of multiplexer circuits 410-1 through 410-4 are coupled to respective bits or lines of a bus or crossbar 412. Multiplexer circuits 410-1 through 410-4 are separately or individually configurable.
Output circuitry 402 further includes a second set of multiplexer circuits 414-1 through 414-4, illustrated here as 4:1 multiplexer circuits. Each multiplexer circuit 414-1 through 414-4 receives all bits of crossbar 412. Each multiplexer circuit 414-1 through 414-4 is separately or individually configurable to output a selectable bit of crossbar 412 to a respective one of output nodes 406-1 through 406-4. In the example of
In
Multiplexer circuitry illustrated in
In the preceding, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the described features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the preceding aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s).
As will be appreciated by one skilled in the art, the embodiments disclosed herein may be embodied as a system, method, or computer program product. Accordingly, aspects may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in this disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various examples of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
