Brian W. Amick

Person

Bedford, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated controller for training memory physical layer interface
- Patent number 9,639,495
- Issue date May 2, 2017
- Advanced Micro Devices, Inc.
- Glenn A. Dearth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for power-up detection for an electrical monit...
- Patent number 9,374,080
- Issue date Jun 21, 2016
- Advanced Micro Devices, Inc.
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic RAM Phy interface with configurable power states
- Patent number 9,274,938
- Issue date Mar 1, 2016
- Advanced Micro Devices, Inc.
- Shawn Searles
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus to reduce memory read latency
- Patent number 8,880,831
- Issue date Nov 4, 2014
- Advanced Micro Devices, Inc.
- Guhan Krishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory diagnostics system and method with hardware-based read/write...
- Patent number 8,607,104
- Issue date Dec 10, 2013
- Advanced Micro Devices, Inc.
- Hanwoo Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus of alternating service modes of an SOI process...
- Patent number 8,373,447
- Issue date Feb 12, 2013
- Advanced Micro Devices, Inc.
- Joseph E. Kidd
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for phase selection acceleration
- Patent number 8,358,158
- Issue date Jan 22, 2013
- Advanced Micro Devices, Inc.
- Brian W. Amick
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic RAM Phy interface with configurable power states
- Patent number 8,356,155
- Issue date Jan 15, 2013
- Advanced Micro Devices, Inc.
- Shawn Searles
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Programmable delay module testing device and methods thereof
- Patent number 8,274,272
- Issue date Sep 25, 2012
- Advanced Micro Devices, Inc.
- Gerald R. Talbot
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for receiver circuit tuning
- Patent number 7,263,628
- Issue date Aug 28, 2007
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to store delay locked loop biasing parameters
- Patent number 7,251,305
- Issue date Jul 31, 2007
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential sense amplifier latch for high common mode input
- Patent number 7,193,447
- Issue date Mar 20, 2007
- Sun Microsystems, Inc.
- Shao H. Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique to enlarge data eyes in wireline communication systems
- Patent number 7,110,461
- Issue date Sep 19, 2006
- Sun Microsystems, Inc.
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generating different delay ratios for a strobe delay
- Patent number 7,109,767
- Issue date Sep 19, 2006
- Sun Microsystems, Inc.
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustment and calibration system for post-fabrication treatment of...
- Patent number 7,106,113
- Issue date Sep 12, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital delay locked loop with extended phase capture range
- Patent number 7,107,475
- Issue date Sep 12, 2006
- Sun Microsystems, Inc.
- Brian Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I/O resonance cancellation circuit based on charge-pumped capacitors
- Patent number 7,062,662
- Issue date Jun 13, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating high speed parallel I/O interfaces based on counters
- Patent number 7,062,688
- Issue date Jun 13, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for quantifying I/O chip/package resonance
- Patent number 7,043,379
- Issue date May 9, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data transmission update technique in low power modes
- Patent number 7,043,683
- Issue date May 9, 2006
- Sun Microsystems, Inc.
- Brian W. Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Round-robin updating for high speed I/O parallel interfaces
- Patent number 7,017,086
- Issue date Mar 21, 2006
- Sun Microsystems, Inc.
- Aninda K. Roy
- G01 - MEASURING TESTING
Information Patent Grant
Low-complexity, high accuracy model of a CPU power distribution system
- Patent number 7,013,254
- Issue date Mar 14, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibration technique for phase locked loop leakage current
- Patent number 6,998,887
- Issue date Feb 14, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-complexity, high accuracy model of a CPU anti-resonance system
- Patent number 6,975,977
- Issue date Dec 13, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method and apparatus for improving sense amplifier performa...
- Patent number 6,975,144
- Issue date Dec 13, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G11 - INFORMATION STORAGE
Information Patent Grant
I/O interface anti-resonance passband shunting technique
- Patent number 6,909,203
- Issue date Jun 21, 2005
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated temperature sensor
- Patent number 6,893,154
- Issue date May 17, 2005
- Sun Microsystems, Inc.
- Spencer M. Gold
- G01 - MEASURING TESTING
Information Patent Grant
SSTL pull-up pre-driver design using regulated power supply
- Patent number 6,873,503
- Issue date Mar 29, 2005
- Sun Microsystems, Inc.
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for reducing a magnitude of a rate of current change of an i...
- Patent number 6,871,290
- Issue date Mar 22, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for I/O resonance compensation
- Patent number 6,842,351
- Issue date Jan 11, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE
- Publication number 20150378603
- Publication date Dec 31, 2015
- Advanced Micro Devices, Inc.
- Glenn A. Dearth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR POWER-UP DETECTION FOR AN ELECTRICAL MONIT...
- Publication number 20150130519
- Publication date May 14, 2015
- Advanced Micro Devices, Inc.
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE
- Publication number 20140325105
- Publication date Oct 30, 2014
- Advanced Micro Devices, Inc.
- Edoardo Prete
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES
- Publication number 20130124806
- Publication date May 16, 2013
- Advanced Micro Devices, Inc.
- Shawn SEARLES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO REDUCE MEMORY READ LATENCY
- Publication number 20120290800
- Publication date Nov 15, 2012
- Guhan Krishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE...
- Publication number 20120159271
- Publication date Jun 21, 2012
- Advanced Micro Devices, Inc.
- Hanwoo Cho
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR PHASE SELECTION ACCELERATION
- Publication number 20120154011
- Publication date Jun 21, 2012
- Advanced Micro Devices, Inc.
- Brian W. Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS...
- Publication number 20120126871
- Publication date May 24, 2012
- Advanced Micro Devices, Inc.
- Joseph E. Kidd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES
- Publication number 20120066445
- Publication date Mar 15, 2012
- Advanced Micro Devices, Inc.
- Shawn Searles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMABLE DELAY MODULE TESTING DEVICE AND METHODS THEREOF
- Publication number 20100201343
- Publication date Aug 12, 2010
- Advanced Micro Devices, Inc.
- Gerald R. Talbot
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for receiver circuit tuning
- Publication number 20040177286
- Publication date Sep 9, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Miller effect compensation technique for DLL phase interpolator design
- Publication number 20040169539
- Publication date Sep 2, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for I/O resonance compensation
- Publication number 20040165406
- Publication date Aug 26, 2004
- Claude R. Gauthier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
System, method and apparatus for improving sense amplifier performa...
- Publication number 20040160243
- Publication date Aug 19, 2004
- SUN MICROSYSTEMS, INC.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data transmission update technique in low power modes
- Publication number 20040156396
- Publication date Aug 12, 2004
- Brian W. Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O interface anti-resonance passband shunting technique
- Publication number 20040150924
- Publication date Aug 5, 2004
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O resonance cancellation circuit based on charge-pumped capacitors
- Publication number 20040123166
- Publication date Jun 24, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for quantifying I/O chip/package resonance
- Publication number 20040088624
- Publication date May 6, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
I/O Power supply resonance compensation technique
- Publication number 20040076025
- Publication date Apr 22, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cascode SSTL output buffer using source followers
- Publication number 20040061526
- Publication date Apr 1, 2004
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SSTL pull-up pre-driver design using regulated power supply
- Publication number 20040057169
- Publication date Mar 25, 2004
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SSTL PULL-DOWN PRE-DRIVER DESIGN USING REGULATED POWER SUPPLY
- Publication number 20040056700
- Publication date Mar 25, 2004
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SSTL voltage translator with dynamic biasing
- Publication number 20040056681
- Publication date Mar 25, 2004
- Brian W. Amick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Source synchronous interface using a dual loop delay locked loop an...
- Publication number 20040047441
- Publication date Mar 11, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Source synchronous interface using variable digital data delay lines
- Publication number 20040046589
- Publication date Mar 11, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibration technique for phase locked loop leakage current
- Publication number 20040033793
- Publication date Feb 19, 2004
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Design-for-test technique for a delay locked loop
- Publication number 20040012420
- Publication date Jan 22, 2004
- Aninda Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Technique to enlarge data eyes in wireline communication systems
- Publication number 20040013203
- Publication date Jan 22, 2004
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Updating high speed parallel I/O interfaces based on counters
- Publication number 20040015751
- Publication date Jan 22, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Round-robin updating for high speed i/o parallel interfaces
- Publication number 20030233608
- Publication date Dec 18, 2003
- Aninda K. Roy
- G01 - MEASURING TESTING

Brian W. Amick

Person

Patents Grantslast 30 patents

Integrated controller for training memory physical layer interface

Method and apparatus for power-up detection for an electrical monit...

Dynamic RAM Phy interface with configurable power states

Method and apparatus to reduce memory read latency

Memory diagnostics system and method with hardware-based read/write...

Method and apparatus of alternating service modes of an SOI process...

Method and apparatus for phase selection acceleration

Dynamic RAM Phy interface with configurable power states

Programmable delay module testing device and methods thereof

Method and apparatus for receiver circuit tuning

Method and apparatus to store delay locked loop biasing parameters

Differential sense amplifier latch for high common mode input

Technique to enlarge data eyes in wireline communication systems

Generating different delay ratios for a strobe delay

Adjustment and calibration system for post-fabrication treatment of...

Digital delay locked loop with extended phase capture range

I/O resonance cancellation circuit based on charge-pumped capacitors

Updating high speed parallel I/O interfaces based on counters

Method for quantifying I/O chip/package resonance

Data transmission update technique in low power modes

Round-robin updating for high speed I/O parallel interfaces

Low-complexity, high accuracy model of a CPU power distribution system

Calibration technique for phase locked loop leakage current

Low-complexity, high accuracy model of a CPU anti-resonance system

System, method and apparatus for improving sense amplifier performa...

I/O interface anti-resonance passband shunting technique

Integrated temperature sensor

SSTL pull-up pre-driver design using regulated power supply

Method for reducing a magnitude of a rate of current change of an i...

Method and apparatus for I/O resonance compensation

Patents Applicationslast 30 patents

INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE

METHOD AND APPARATUS FOR POWER-UP DETECTION FOR AN ELECTRICAL MONIT...

MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE

DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES

METHOD AND APPARATUS TO REDUCE MEMORY READ LATENCY

MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE...

METHOD AND APPARATUS FOR PHASE SELECTION ACCELERATION

METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS...

DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES

PROGRAMABLE DELAY MODULE TESTING DEVICE AND METHODS THEREOF

Method and apparatus for receiver circuit tuning

Miller effect compensation technique for DLL phase interpolator design

Method and apparatus for I/O resonance compensation

System, method and apparatus for improving sense amplifier performa...

Data transmission update technique in low power modes

I/O interface anti-resonance passband shunting technique

I/O resonance cancellation circuit based on charge-pumped capacitors

Method for quantifying I/O chip/package resonance

I/O Power supply resonance compensation technique

Cascode SSTL output buffer using source followers

SSTL pull-up pre-driver design using regulated power supply

SSTL PULL-DOWN PRE-DRIVER DESIGN USING REGULATED POWER SUPPLY

SSTL voltage translator with dynamic biasing

Source synchronous interface using a dual loop delay locked loop an...

Source synchronous interface using variable digital data delay lines

Calibration technique for phase locked loop leakage current

Design-for-test technique for a delay locked loop

Technique to enlarge data eyes in wireline communication systems

Updating high speed parallel I/O interfaces based on counters

Round-robin updating for high speed i/o parallel interfaces