Brion L. Keller

Person

Birghamton, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for diagnosing failure locations in electronic ci...
- Patent number 9,864,004
- Issue date Jan 9, 2018
- Cadence Design Systems, Inc.
- Sameer Chakravarthy Chillarige
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for efficient hierarchical chip testing and di...
- Patent number 9,404,969
- Issue date Aug 2, 2016
- Cadence Design Systems, Inc.
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for providing efficient on-product clock generati...
- Patent number 8,887,019
- Issue date Nov 11, 2014
- Cadence Design Systems, Inc.
- Karishna Chakravadhanula
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for automated extraction of a design for test...
- Patent number 8,732,632
- Issue date May 20, 2014
- Cadence Design Systems, Inc.
- Brion Keller
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for reducing switching activity during scan-load...
- Patent number 8,468,404
- Issue date Jun 18, 2013
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G01 - MEASURING TESTING
Information Patent Grant
Fault modeling for state retention logic
- Patent number 8,296,703
- Issue date Oct 23, 2012
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power scan test for integrated circuits
- Patent number 7,693,676
- Issue date Apr 6, 2010
- Cadence Design Systems, Inc.
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Channel masking during integrated circuit testing
- Patent number 7,523,370
- Issue date Apr 21, 2009
- Cadence Design Systems, Inc.
- Brion Keller
- G01 - MEASURING TESTING
Information Patent Grant
System and method for performing logic failure diagnosis using mult...
- Patent number 7,487,420
- Issue date Feb 3, 2009
- Cadence Design Systems Inc.
- Brion Keller
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement for testing semiconductor chips while incorporated on a...
- Patent number 7,435,990
- Issue date Oct 14, 2008
- International Business Machines Corporation
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement for testing semiconductor chips while incorporated on a...
- Patent number 7,381,986
- Issue date Jun 3, 2008
- International Business Machines Corporation
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for reducing test data volume in the testing of l...
- Patent number 7,103,816
- Issue date Sep 5, 2006
- Cadence Design Systems, Inc.
- Frank O. Distler
- G01 - MEASURING TESTING
Information Patent Grant
Method for reducing switching activity during a scan operation with...
- Patent number 6,986,090
- Issue date Jan 10, 2006
- International Business Machines Corporation
- David J. Hathaway
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing integrated logic circuits
- Patent number 6,804,803
- Issue date Oct 12, 2004
- International Business Machines Corporation
- Carl F. Barnhart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for reducing test data volume in the testing of logic products
- Patent number 6,782,501
- Issue date Aug 24, 2004
- Cadence Design Systems, Inc.
- Frank O. Distler
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic random LBIST
- Patent number 6,708,305
- Issue date Mar 16, 2004
- International Business Machines Corporation
- L. Owen Farnsworth
- G01 - MEASURING TESTING
Information Patent Grant
Real-time decoder for scan test patterns
- Patent number 6,611,933
- Issue date Aug 26, 2003
- International Business Machines Corporation
- Bernd Koenemann
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical pattern faults for describing logic circuit failure me...
- Patent number 5,546,408
- Issue date Aug 13, 1996
- International Business Machines Corporation
- Brion L. Keller
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR PROVIDING EFFICIENT ON-PRODUCT CLOCK GENERATI...
- Publication number 20120124423
- Publication date May 17, 2012
- Cadence Design Systems Inc.
- KRISHNA CHAKRAVADHANULA
- G01 - MEASURING TESTING
Information Patent Application
Arrangement for testing semiconductor chips while incorporated on a...
- Publication number 20060284174
- Publication date Dec 21, 2006
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Application
System and method for performing logic failure diagnosis using mult...
- Publication number 20060200719
- Publication date Sep 7, 2006
- Cadence Design Systems, Inc.
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR COMPACT SCAN TESTING
- Publication number 20040139377
- Publication date Jul 15, 2004
- International Business Machines Corporation
- Carl F. Barnhart
- G01 - MEASURING TESTING
Information Patent Application
AN ARRANGEMENT FOR TESTING SEMICONDUCTOR CHIPS WHILE INCORPORATED O...
- Publication number 20040135231
- Publication date Jul 15, 2004
- International Business Machines Corporation
- Brion L. Keller
- G01 - MEASURING TESTING
Information Patent Application
Method for reducing switching activity during a scan operation with...
- Publication number 20030182604
- Publication date Sep 25, 2003
- International Business Machines Corporation
- David J. Hathaway
- G01 - MEASURING TESTING
Information Patent Application
Method for testing integrated logic circuits
- Publication number 20020147559
- Publication date Oct 10, 2002
- Carl F. Barnhart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for reducing test data volume in the testing of l...
- Publication number 20020099991
- Publication date Jul 25, 2002
- International Business Machines Corporation
- Frank O. Distler
- G01 - MEASURING TESTING
Information Patent Application
System for reducing test data volume in the testing of logic products
- Publication number 20020099992
- Publication date Jul 25, 2002
- International Business Machines Corporation
- Frank O. Distler
- G01 - MEASURING TESTING

Brion L. Keller

Person

Patents Grantslast 30 patents

System and method for diagnosing failure locations in electronic ci...

Method and apparatus for efficient hierarchical chip testing and di...

Method and system for providing efficient on-product clock generati...

Method and apparatus for automated extraction of a design for test...

Method and system for reducing switching activity during scan-load...

Fault modeling for state retention logic

Low power scan test for integrated circuits

Channel masking during integrated circuit testing

System and method for performing logic failure diagnosis using mult...

Arrangement for testing semiconductor chips while incorporated on a...

Arrangement for testing semiconductor chips while incorporated on a...

Method and system for reducing test data volume in the testing of l...

Method for reducing switching activity during a scan operation with...

Method for testing integrated logic circuits

System for reducing test data volume in the testing of logic products

Deterministic random LBIST

Real-time decoder for scan test patterns

Hierarchical pattern faults for describing logic circuit failure me...

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR PROVIDING EFFICIENT ON-PRODUCT CLOCK GENERATI...

Arrangement for testing semiconductor chips while incorporated on a...

System and method for performing logic failure diagnosis using mult...

METHOD AND APPARATUS FOR COMPACT SCAN TESTING

AN ARRANGEMENT FOR TESTING SEMICONDUCTOR CHIPS WHILE INCORPORATED O...

Method for reducing switching activity during a scan operation with...

Method for testing integrated logic circuits

Method and system for reducing test data volume in the testing of l...

System for reducing test data volume in the testing of logic products