Bruce Gieseke

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple write during simultaneous memory access of a multi-port me...
- Patent number RE46474
- Issue date Jul 11, 2017
- eASIC Corporation
- Hui Hui Ngu
Information Patent Grant
Multiple write during simultaneous memory access of a multi-port me...
- Patent number 8,848,479
- Issue date Sep 30, 2014
- eASIC Corporation
- Hui H. Ngu
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory with shadow memory cell
- Patent number 6,807,107
- Issue date Oct 19, 2004
- Advanced Micro Devices, Inc.
- William A. McGee
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline latching in semiconductor memories
- Patent number 6,798,712
- Issue date Sep 28, 2004
- Advanced Micro Devices, Inc.
- Bruce Alan Gieseke
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for compacting an instruction queue
- Patent number 6,704,856
- Issue date Mar 9, 2004
- Hewlett-Packard Development Company, L.P.
- James A. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for mapping instructions using a set of valid and invalid...
- Patent number 6,675,288
- Issue date Jan 6, 2004
- Hewlett-Packard Development Company L.P.
- James Arthur Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silicon on insulator logic circuit utilizing diode switching elements
- Patent number 6,433,389
- Issue date Aug 13, 2002
- Advanced Micro Devices, Inc.
- Bruce Alan Gieseke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for mapping instructions using a set of valid and invalid lo...
- Patent number 6,405,304
- Issue date Jun 11, 2002
- Compaq Information Technologies Group, L.P.
- James Arthur Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling 16-bit addressing in a processor
- Patent number 6,363,471
- Issue date Mar 26, 2002
- Advanced Micro Devices, Inc.
- Stephan G. Meier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbiter system for central processing unit having dual dominoed enc...
- Patent number 6,249,855
- Issue date Jun 19, 2001
- Compaq Computer Corporation
- James A. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded input logic in a high input impedance strobed CMOS differe...
- Patent number 6,195,377
- Issue date Feb 27, 2001
- Digital Equipment Corporation
- Shane Lewis Bell
- G11 - INFORMATION STORAGE
Information Patent Grant
Register scoreboard logic with register read availability signal to...
- Patent number 6,167,508
- Issue date Dec 26, 2000
- Compaq Computer Corporation
- James A. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory having memory cells storing don't care s...
- Patent number 5,890,201
- Issue date Mar 30, 1999
- Digital Equipment Corporation
- Edward J. McLellan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translating buffer and method for translating addresses utilizing i...
- Patent number 5,784,709
- Issue date Jul 21, 1998
- Digital Equipment Corporation
- Edward J. McLellan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory having a pair of memory cells storing do...
- Patent number 5,568,415
- Issue date Oct 22, 1996
- Digital Equipment Corporation
- Edward J. McLellan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE WRITE DURING SIMULTANEOUS MEMORY ACCESS OF A MULTI-PORT ME...
- Publication number 20120243285
- Publication date Sep 27, 2012
- eASIC Corporation
- Hui H. Ngu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR MONOLITHIC POWER GATING ON AN INTEGRATED CIRCUIT
- Publication number 20120105129
- Publication date May 3, 2012
- Samuel D. Naffziger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device and method of manufacture
- Publication number 20050167733
- Publication date Aug 4, 2005
- Advanced Micro Devices, Inc.
- William A. McGee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for compacting a queue
- Publication number 20040098566
- Publication date May 20, 2004
- James A. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wordline latching in semiconductor memories
- Publication number 20040004901
- Publication date Jan 8, 2004
- Bruce Alan Gieseke
- G11 - INFORMATION STORAGE
Information Patent Application
Method for mapping instructions using a set of valid and invalid lo...
- Publication number 20020156997
- Publication date Oct 24, 2002
- James Arthur Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MAPPING INSTRUCTIONS USING A SET OF VALID AND INVALID LO...
- Publication number 20020069346
- Publication date Jun 6, 2002
- JAMES ARTHUR FARRELL
- G06 - COMPUTING CALCULATING COUNTING

Bruce Gieseke

Person

Patents Grantslast 30 patents

Multiple write during simultaneous memory access of a multi-port me...

Multiple write during simultaneous memory access of a multi-port me...

Semiconductor memory with shadow memory cell

Wordline latching in semiconductor memories

Method for compacting an instruction queue

Apparatus for mapping instructions using a set of valid and invalid...

Silicon on insulator logic circuit utilizing diode switching elements

Method for mapping instructions using a set of valid and invalid lo...

Mechanism for handling 16-bit addressing in a processor

Arbiter system for central processing unit having dual dominoed enc...

Embedded input logic in a high input impedance strobed CMOS differe...

Register scoreboard logic with register read availability signal to...

Content addressable memory having memory cells storing don't care s...

Translating buffer and method for translating addresses utilizing i...

Content addressable memory having a pair of memory cells storing do...

Patents Applicationslast 30 patents

MULTIPLE WRITE DURING SIMULTANEOUS MEMORY ACCESS OF A MULTI-PORT ME...

APPARATUS FOR MONOLITHIC POWER GATING ON AN INTEGRATED CIRCUIT

Memory device and method of manufacture

Method and apparatus for compacting a queue

Wordline latching in semiconductor memories

Method for mapping instructions using a set of valid and invalid lo...

METHOD FOR MAPPING INSTRUCTIONS USING A SET OF VALID AND INVALID LO...