Patent Application
20120105129
1. Technical Field
This disclosure relates to integrated circuits and, more particularly, to a power gating mechanism on the integrated circuits.
2. Description of the Related Art
Electronic devices and particularly those with modern processors are capable of consuming a great deal of power. In an effort to conserve battery life, in many systems it is becoming commonplace to turn off components that are not being used. Power gating, which is the term used to describe completely removing the voltage reference or the circuit ground reference from the component, is being widely used. This is in contrast to simply stopping the clock on a processor, for example. However, although power gating may be one of the most effective ways to reduce power consumption of a component, conventional power gating has some drawbacks.
One such drawback is the necessity of instantiating power gating transistors into the logic portion of the component. In many cases these power gating transistors are distributed throughout the logic of the component. Another drawback is the use of abnormally thick (and expensive) on-die metallization to redistribute current from the distant distributed power gate devices to the power consuming circuitry.
Various embodiments of an apparatus for power gating on an integrated circuit are disclosed. In one embodiment, the apparatus includes an integrated circuit package with a first voltage reference plane and a second voltage reference plane, and an integrated circuit that includes a circuit block such as a processor core, for example, and a switch block. The first and second voltage reference planes may be electrically isolated from one another. The switch block may include a plurality of switches arranged in a ring surrounding the circuit block. The first voltage reference plane may be electrically coupled between an external voltage reference such as VSS, for example, and the plurality of switches, and the second voltage reference plane may be electrically coupled between the plurality of switches and the circuit block. The second voltage reference plane may also be configured to distribute an electric current throughout the circuit block. In addition, each of the switches is configured to interrupt an electrical path between the first reference voltage plane and the circuit block in response to a control signal.
Specific embodiments are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the claims to the particular embodiments disclosed, even where only a single embodiment is described with respect to a particular feature. On the contrary, the intention is to cover all modifications, equivalents and alternatives that would be apparent to a person skilled in the art having the benefit of this disclosure. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise.
As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to.
Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph six, interpretation for that unit/circuit/component.
Turning now to
As will be described in greater detail below, the PG ring segments 14 may include a plurality of switches (e.g., transistors) that may be coupled between the circuit ground reference (VSS) and/or the voltage reference/supply voltage (VDD) supplied through an IC package (not shown) and the VSS or the VDD connections on the IC core logic portion 12. As shown, the PG ring segments 14 are arranged around the periphery of the IC core logic 12, and are thus not part of the IC core logic 12.
In one embodiment, the PG ring segments 14 may be controlled by control logic that may be employed outside of the PG ring segments 14. For example, if the IC core logic 12 and the PG ring segments 14 are part of a larger IC 10 having additional components such as in a system on a chip (SOC), the SOC may include the control logic that causes the switches in the PG ring segments 14 to turn on and off.
It is noted that the IC core logic 12 may be representative of any type integrated circuit logic. More particularly, it is contemplated that the IC core logic 12 may be any logic block that may need to be powered on and off independent of other logic blocks, and/or other circuit components.
Referring to
As described above in conjunction with the description of
Many IC packages include one or more voltage reference planes that are used to distribute VDD and VSS across an IC die such as IC die 10. Accordingly, as shown in
In the illustrated embodiment the external VSS connections are coupled together and to the Pkg RVSS plane 235. This provides an external distribution path for VSS within a portion of the package 215. In addition, the connections in the Pkg VSS plane 225 are coupled together and to the core logic 12 of the IC die 10 when the package 215 is bonded to the IC die 10. Thus, the Pkg VSS plane 225 provides a distribution path for the VSS current on the IC die 10 in the other portion of the package 215. However, as shown, the Pkg RVSS plane 235 and the Pkg VSS plane 225 are electrically isolated from one another. Accordingly, the transistors 217 and 219, when conducting, provide a VSS path between the Pkg RVSS plane 235 and the Pkg VSS plane 225. Thus, in one embodiment, when it is desirable to power off the IC die 10, the transistors 217 and 219 may be turned off through control signals (not shown) provided external to the footers 214 and the core 12.
It is noted that although
Turning to
As shown, the Pkg RVSS plane 235 and a Pkg VSS plane 225 are not electrically connected in the package. Accordingly, as described above in conjunction with the description of
Referring to
It is also noted that, a processing node such as node 400 may include any number of processor cores, in various embodiments. It is further noted that processor node 400 may include many other components that have been omitted here for simplicity. For example, in various embodiments processing node 400 may include an integral memory controller and various communication interfaces for communicating with other nodes, and I/O devices.
In one embodiment, node controller 420 may include various interconnection circuits (not shown) for interconnecting processor cores 412A-41D to each other, to other nodes, and to a system memory (not shown).
As described above, the power gating rings 414 may be used to independently power on and off the processor cores 412. Accordingly, in one embodiment, the node controller 420 may also include logic to control the power gating rings 414, and thus to power on and off the individual processor cores 412.
Thus, the above embodiments may provide a mechanism that enables low cost power gating of small or large complex IP (such as processor cores—e.g., central processing cores, graphics cores, digital signal processing cores, etc.) with a relatively simple design process (the power gating ring), and no additional costs in either on-die metal layers, or additional package layers since the existing package power/ground planes may be simply subdivided into gated (e.g., 225) and non-gated (e.g., 235) regions.
Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
