Bruce Joseph Whitefield

Person

Camas, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clamping mechanism for a two wheel panel dolly
- Patent number 8,899,599
- Issue date Dec 2, 2014
- Bruce Joseph Whitefield
- B62 - LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
Information Patent Grant
Yield profile manipulator
- Patent number 7,930,655
- Issue date Apr 19, 2011
- LSI Corporation
- ChandraSekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer edge expose alignment method
- Patent number 7,799,166
- Issue date Sep 21, 2010
- LSI Corporation
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for calculating high-resolution wafer parameter profiles
- Patent number 7,653,523
- Issue date Jan 26, 2010
- LSI Corporation
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanotube fuse structure
- Patent number 7,598,127
- Issue date Oct 6, 2009
- Nantero, Inc.
- Bruce J. Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage contrast monitor for integrated circuit defects
- Patent number 7,560,292
- Issue date Jul 14, 2009
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for wafer patterning to reduce edge exclusion zone
- Patent number 7,460,211
- Issue date Dec 2, 2008
- LSI Corporation
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Yield profile manipulator
- Patent number 7,395,522
- Issue date Jul 1, 2008
- LSI Corporation
- ChandraSekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage contrast monitor for integrated circuit defects
- Patent number 7,323,768
- Issue date Jan 29, 2008
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Surface coordinate system
- Patent number 7,315,360
- Issue date Jan 1, 2008
- LSI Logic Corporation
- Bruce J. Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Wafer edge structure measurement method
- Patent number 7,312,880
- Issue date Dec 25, 2007
- LSI Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Pattern detection for integrated circuit substrates
- Patent number 7,277,813
- Issue date Oct 2, 2007
- State of Oregon University Portland State
- Bruce J. Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic edge bead removal
- Patent number 7,183,181
- Issue date Feb 27, 2007
- LSI Logic Corporation
- Xiao Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern component analysis and manipulation
- Patent number 7,137,098
- Issue date Nov 14, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of wafer patterning for reducing edge exclusion zone
- Patent number 7,074,710
- Issue date Jul 11, 2006
- LSI Logic Corporation
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Parametric outlier detection
- Patent number 7,062,415
- Issue date Jun 13, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrate profile analysis
- Patent number 7,039,556
- Issue date May 2, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Substrate contact analysis
- Patent number 7,013,192
- Issue date Mar 14, 2006
- LSI Logic Corporation
- Bruce J. Whitefield
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method of mapping logic failures in an integrated circuit die
- Patent number 6,986,112
- Issue date Jan 10, 2006
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Method and control system for improving CMP process by detecting an...
- Patent number 6,971,944
- Issue date Dec 6, 2005
- LSI Logic Corporation
- Michael J. Berman
- B24 - GRINDING POLISHING
Information Patent Grant
Method of detecting spatially correlated variations in a parameter...
- Patent number 6,943,042
- Issue date Sep 13, 2005
- LSI Logic Corporation
- Robert Madge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage contrast monitor for integrated circuit defects
- Patent number 6,936,920
- Issue date Aug 30, 2005
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Grant
Method of detecting spatially correlated variations in a parameter...
- Patent number 6,787,379
- Issue date Sep 7, 2004
- LSI Logic Corporation
- Robert Madge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for inhibiting edge peeling of coating on semiconductor sub...
- Patent number 6,767,692
- Issue date Jul 27, 2004
- LSI Logic Corporation
- Roger Young
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Integrated process tool monitoring system for semiconductor fabrica...
- Patent number 6,650,958
- Issue date Nov 18, 2003
- LSI Logic Corporation
- Attila Balazs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Key hole filling
- Patent number 6,645,857
- Issue date Nov 11, 2003
- LSI Logic Corporation
- Bruce J. Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for removing photoresist edge beads from thin film substr...
- Patent number 6,614,507
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Roger Y. B. Young
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Process control system
- Patent number 6,512,985
- Issue date Jan 28, 2003
- LSI Logic Corporation
- Bruce J. Whitefield
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for removing photoresist edge beads from thin...
- Patent number 6,495,312
- Issue date Dec 17, 2002
- LSI Logic Corporation
- Roger Y. B. Young
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and structure for improving patterning design for processing
- Patent number 5,654,897
- Issue date Aug 5, 1997
- LSI Logic Corporation
- Prabhakar P. Tripathi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Clamping Mechanism for a Two Wheel Panel Dolly
- Publication number 20140015211
- Publication date Jan 16, 2014
- Bruce Joseph Whitefield
- B62 - LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
Information Patent Application
Yield Profile Manipulator
- Publication number 20080216048
- Publication date Sep 4, 2008
- LSI Corporation
- ChandraSekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
- Publication number 20080061805
- Publication date Mar 13, 2008
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Application
Nanotube fuse structure
- Publication number 20060258122
- Publication date Nov 16, 2006
- Bruce J. Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE
- Publication number 20060191634
- Publication date Aug 31, 2006
- Bruce Whitefield
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Pattern detection for integrated circuit substrates
- Publication number 20060190207
- Publication date Aug 24, 2006
- Bruce J. Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE
- Publication number 20060094246
- Publication date May 4, 2006
- LSI Logic Corporation
- Bruce Whitefield
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Metal removal from solvent
- Publication number 20060076036
- Publication date Apr 13, 2006
- Bruce J. Whitefield
- B08 - CLEANING
Information Patent Application
Surface coordinate system
- Publication number 20060073617
- Publication date Apr 6, 2006
- Bruce J. Whitefield
- G01 - MEASURING TESTING
Information Patent Application
Dynamic edge bead removal
- Publication number 20060073703
- Publication date Apr 6, 2006
- Xiao Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Defect monitoring system
- Publication number 20060069659
- Publication date Mar 30, 2006
- Michael S. Gatov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Substrate edge scribe
- Publication number 20060065985
- Publication date Mar 30, 2006
- Michael J. Berman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer edge expose alignment method
- Publication number 20060060299
- Publication date Mar 23, 2006
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pattern component analysis and manipulation
- Publication number 20060059452
- Publication date Mar 16, 2006
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wafer edge structure measurement method
- Publication number 20060044571
- Publication date Mar 2, 2006
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Application
Parametric outlier detection
- Publication number 20060047485
- Publication date Mar 2, 2006
- Bruce J. Whitefield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Substrate profile analysis
- Publication number 20050288896
- Publication date Dec 29, 2005
- Bruce J. Whitefield
- G05 - CONTROLLING REGULATING
Information Patent Application
SUBSTRATE CONTACT ANALYSIS
- Publication number 20050278678
- Publication date Dec 15, 2005
- Bruce J. Whitefield
- G05 - CONTROLLING REGULATING
Information Patent Application
Yield profile manipulator
- Publication number 20050229144
- Publication date Oct 13, 2005
- Chandra Sekhar Desu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage contrast monitor for integrated circuit defects
- Publication number 20050224963
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND CONTROL SYSTEM FOR IMPROVING CMP PROCESS BY DETECTING AN...
- Publication number 20050181706
- Publication date Aug 18, 2005
- Michael J. Berman
- B24 - GRINDING POLISHING
Information Patent Application
Method for calculating high-resolution wafer parameter profiles
- Publication number 20050132308
- Publication date Jun 16, 2005
- Bruce Whitefield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Voltage contrast monitor for integrated circuit defects
- Publication number 20050046019
- Publication date Mar 3, 2005
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Application
Method of mapping logic failures in an integrated circuit die
- Publication number 20050028115
- Publication date Feb 3, 2005
- Bruce Whitefield
- G01 - MEASURING TESTING
Information Patent Application
Method of detecting spatially correlated variations in a parameter...
- Publication number 20040033635
- Publication date Feb 19, 2004
- Robert Madge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus for removing photoresist edge beads from thin film substr...
- Publication number 20030031959
- Publication date Feb 13, 2003
- Roger Y.B. Young
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Bruce Joseph Whitefield

Person

Patents Grantslast 30 patents

Clamping mechanism for a two wheel panel dolly

Yield profile manipulator

Wafer edge expose alignment method

Method for calculating high-resolution wafer parameter profiles

Nanotube fuse structure

Voltage contrast monitor for integrated circuit defects

Apparatus for wafer patterning to reduce edge exclusion zone

Yield profile manipulator

Voltage contrast monitor for integrated circuit defects

Surface coordinate system

Wafer edge structure measurement method

Pattern detection for integrated circuit substrates

Dynamic edge bead removal

Pattern component analysis and manipulation

Method of wafer patterning for reducing edge exclusion zone

Parametric outlier detection

Substrate profile analysis

Substrate contact analysis

Method of mapping logic failures in an integrated circuit die

Method and control system for improving CMP process by detecting an...

Method of detecting spatially correlated variations in a parameter...

Voltage contrast monitor for integrated circuit defects

Method of detecting spatially correlated variations in a parameter...

Process for inhibiting edge peeling of coating on semiconductor sub...

Integrated process tool monitoring system for semiconductor fabrica...

Key hole filling

Apparatus for removing photoresist edge beads from thin film substr...

Process control system

Method and apparatus for removing photoresist edge beads from thin...

Method and structure for improving patterning design for processing

Patents Applicationslast 30 patents

Clamping Mechanism for a Two Wheel Panel Dolly

Yield Profile Manipulator

VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS

Nanotube fuse structure

APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE

Pattern detection for integrated circuit substrates

METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE

Metal removal from solvent

Surface coordinate system

Dynamic edge bead removal

Defect monitoring system

Substrate edge scribe

Wafer edge expose alignment method

Pattern component analysis and manipulation

Wafer edge structure measurement method

Parametric outlier detection

Substrate profile analysis

SUBSTRATE CONTACT ANALYSIS

Yield profile manipulator

Voltage contrast monitor for integrated circuit defects

METHOD AND CONTROL SYSTEM FOR IMPROVING CMP PROCESS BY DETECTING AN...

Method for calculating high-resolution wafer parameter profiles

Voltage contrast monitor for integrated circuit defects

Method of mapping logic failures in an integrated circuit die

Method of detecting spatially correlated variations in a parameter...

Apparatus for removing photoresist edge beads from thin film substr...