Ceredig Roberts

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming a DRAM array of devices with vertically integrate...
- Patent number 8,716,116
- Issue date May 6, 2014
- Micron Technology, Inc.
- Kunal Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device
- Patent number 7,935,999
- Issue date May 3, 2011
- Micron Technology, Inc.
- Gordon A. Haller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a memory device
- Patent number 7,687,342
- Issue date Mar 30, 2010
- Micron Technology, Inc.
- Gordon A. Haller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor structure for two-transistor DRAM memory cell and method...
- Patent number 7,488,664
- Issue date Feb 10, 2009
- Micron Technology, Inc.
- Keith Cook
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device to reduce gate-induced drain leakage (GIDL) curre...
- Patent number 7,247,919
- Issue date Jul 24, 2007
- Micron Technology, Inc.
- Chandra V. Mouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Residue free overlay target
- Patent number 6,914,017
- Issue date Jul 5, 2005
- Micron Technology, Inc.
- Pary Baluswamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Raised-lines overlay semiconductor targets and method of making the...
- Patent number 6,822,342
- Issue date Nov 23, 2004
- Micron Technology, Inc.
- Pary Baluswamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device to reduce gate-induced drain leakage (GIDL) curre...
- Patent number 6,693,012
- Issue date Feb 17, 2004
- Micron Technology, Inc.
- Chandra V. Mouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making straight wall containers and the resultant containers
- Patent number 6,541,809
- Issue date Apr 1, 2003
- Micron Technology, Inc.
- Gurtej S. Sandhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide etching method and structures resulting from same
- Patent number 6,531,728
- Issue date Mar 11, 2003
- Micron Technology, Inc.
- Scott J. DeBoer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming transistors in a peripheral circuit of a semicond...
- Patent number 6,271,073
- Issue date Aug 7, 2001
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide etching method and structures resulting from same
- Patent number 6,258,729
- Issue date Jul 10, 2001
- Micron Technology, Inc.
- Scott J. DeBoer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming transistors in a peripheral circuit of a semicond...
- Patent number 6,252,268
- Issue date Jun 26, 2001
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making straight wall containers and the resultant containers
- Patent number 6,235,639
- Issue date May 22, 2001
- Micron Technology, Inc.
- Gurtej S. Sandhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high aspect ratio structures for semiconductor de...
- Patent number 6,204,143
- Issue date Mar 20, 2001
- Micron Technology Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning cavities and enhanced cavity shapes for semic...
- Patent number 6,190,989
- Issue date Feb 20, 2001
- Micron Technology, Inc.
- Ceredig Roberts
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dual-masked field isolation
- Patent number 6,103,020
- Issue date Aug 15, 2000
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device and method of forming transistors in a...
- Patent number 6,040,209
- Issue date Mar 21, 2000
- Micron Technology
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell employing substantially vertically elongated pull-up resi...
- Patent number 5,995,411
- Issue date Nov 30, 1999
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Facet etch for improved step coverage of integrated circuit contacts
- Patent number 5,985,767
- Issue date Nov 16, 1999
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sram cell employing substantially vertically elongated pull-up resi...
- Patent number 5,969,994
- Issue date Oct 19, 1999
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell employing substantially vertically elongated pull-up resi...
- Patent number 5,943,269
- Issue date Aug 24, 1999
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-masked isolation
- Patent number 5,909,630
- Issue date Jun 1, 1999
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Facet etch for improved step coverage of integrated circuit contacts
- Patent number 5,861,344
- Issue date Jan 19, 1999
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SCRAM cell employing substantially vertically elongated pull-up res...
- Patent number 5,844,835
- Issue date Dec 1, 1998
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell employing substantially vertically elongated pull-up resi...
- Patent number 5,844,838
- Issue date Dec 1, 1998
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell employing substantially vertically elongated pull-up resi...
- Patent number 5,808,941
- Issue date Sep 15, 1998
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-masked field isolation
- Patent number 5,789,306
- Issue date Aug 4, 1998
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell employing substantially vertically elongated pull-up resi...
- Patent number 5,751,630
- Issue date May 12, 1998
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM cell employing substantially vertically elongated pull-up resi...
- Patent number 5,732,023
- Issue date Mar 24, 1998
- Micron Technology, Inc.
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING A DRAM ARRAY OF DEVICES WITH VERTICALLY INTEGRATE...
- Publication number 20140231894
- Publication date Aug 21, 2014
- Micron Technology, Inc.
- Kunal Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming a DRAM Array of Devices with Vertically Integrate...
- Publication number 20110220994
- Publication date Sep 15, 2011
- Micron Technology, Inc.
- Kunal Parekh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Of Manufacturing A Memory Device
- Publication number 20100148249
- Publication date Jun 17, 2010
- Micron Technology, Inc.
- Gordon A. Haller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell layout and process flow
- Publication number 20070045712
- Publication date Mar 1, 2007
- Gordon A. Haller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capacitor structure for two-transistor dram memory cell and method...
- Publication number 20070034928
- Publication date Feb 15, 2007
- Micron Technology, Inc.
- Keith Cook
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and device to reduce gate-induced drain leakage (GIDL) curre...
- Publication number 20060263964
- Publication date Nov 23, 2006
- Chandra V. Mouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Raised-lines overlay semiconductor targets and method of making the...
- Publication number 20060017074
- Publication date Jan 26, 2006
- Pary Baluswamy
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Raised-lines overlay semiconductor targets and method of making the...
- Publication number 20050070069
- Publication date Mar 31, 2005
- Pary Baluswamy
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and device to reduce gate-induced drain leakage (GIDL) curre...
- Publication number 20020050621
- Publication date May 2, 2002
- Chandra V. Mouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Residue-free overlay target
- Publication number 20020036332
- Publication date Mar 28, 2002
- Pary Baluswamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Oxide etching method and structures resulting from same
- Publication number 20010038111
- Publication date Nov 8, 2001
- Micron Technology, Inc.
- Scott J. DeBoer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming high aspect ratio structures for semiconductor de...
- Publication number 20010002710
- Publication date Jun 7, 2001
- Ceredig Roberts
- H01 - BASIC ELECTRIC ELEMENTS

Ceredig Roberts

Person

Patents Grantslast 30 patents

Method of forming a DRAM array of devices with vertically integrate...

Memory device

Method of manufacturing a memory device

Capacitor structure for two-transistor DRAM memory cell and method...

Method and device to reduce gate-induced drain leakage (GIDL) curre...

Residue free overlay target

Raised-lines overlay semiconductor targets and method of making the...

Method and device to reduce gate-induced drain leakage (GIDL) curre...

Method of making straight wall containers and the resultant containers

Oxide etching method and structures resulting from same

Method of forming transistors in a peripheral circuit of a semicond...

Oxide etching method and structures resulting from same

Method of forming transistors in a peripheral circuit of a semicond...

Method of making straight wall containers and the resultant containers

Method of forming high aspect ratio structures for semiconductor de...

Method for patterning cavities and enhanced cavity shapes for semic...

Dual-masked field isolation

Semiconductor memory device and method of forming transistors in a...

SRAM cell employing substantially vertically elongated pull-up resi...

Facet etch for improved step coverage of integrated circuit contacts

Sram cell employing substantially vertically elongated pull-up resi...

SRAM cell employing substantially vertically elongated pull-up resi...

Dual-masked isolation

Facet etch for improved step coverage of integrated circuit contacts

SCRAM cell employing substantially vertically elongated pull-up res...

SRAM cell employing substantially vertically elongated pull-up resi...

SRAM cell employing substantially vertically elongated pull-up resi...

Dual-masked field isolation

SRAM cell employing substantially vertically elongated pull-up resi...

SRAM cell employing substantially vertically elongated pull-up resi...

Patents Applicationslast 30 patents

METHOD OF FORMING A DRAM ARRAY OF DEVICES WITH VERTICALLY INTEGRATE...

Method of Forming a DRAM Array of Devices with Vertically Integrate...

Method Of Manufacturing A Memory Device

Memory cell layout and process flow

Capacitor structure for two-transistor dram memory cell and method...

Method and device to reduce gate-induced drain leakage (GIDL) curre...

Raised-lines overlay semiconductor targets and method of making the...

Raised-lines overlay semiconductor targets and method of making the...

Method and device to reduce gate-induced drain leakage (GIDL) curre...

Residue-free overlay target

Oxide etching method and structures resulting from same

Method of forming high aspect ratio structures for semiconductor de...