Chad A. Adams

Person

Byron, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory interface latch with integrated write-through and fence func...
- Patent number 10,916,323
- Issue date Feb 9, 2021
- International Business Machines Corporation
- Elizabeth L. Gerhard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface latch with integrated write-through and fence func...
- Patent number 10,381,098
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Elizabeth L. Gerhard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface latch with integrated write-through function
- Patent number 10,229,748
- Issue date Mar 12, 2019
- International Business Machines Corporation
- Elizabeth L. Gerhard
- G11 - INFORMATION STORAGE
Information Patent Grant
Deep sleep wakeup of multi-bank memory
- Patent number 9,251,869
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Deep sleep wakeup of multi-bank memory
- Patent number 9,183,896
- Issue date Nov 10, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Fine granularity power gating
- Patent number 9,183,906
- Issue date Nov 10, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing sense amplifier for sensing local write driver with bo...
- Patent number 9,087,607
- Issue date Jul 21, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM global precharge, discharge, and sense
- Patent number 9,007,857
- Issue date Apr 14, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM global precharge, discharge, and sense
- Patent number 9,007,858
- Issue date Apr 14, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array pulse width control
- Patent number 8,754,691
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Chad A. Adams
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Implementing low power write disabled local evaluation for SRAM
- Patent number 8,659,937
- Issue date Feb 25, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing supply and source write assist for SRAM arrays
- Patent number 8,593,890
- Issue date Nov 26, 2013
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing column redundancy steering for memories with wordline...
- Patent number 8,451,668
- Issue date May 28, 2013
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Active bit line droop for read assist
- Patent number 8,331,180
- Issue date Dec 11, 2012
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Single supply sub VDD bit-line precharge SRAM and method for level...
- Patent number 8,279,687
- Issue date Oct 2, 2012
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter for use with memory arrays
- Patent number 8,274,848
- Issue date Sep 25, 2012
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing write assist for static rando...
- Patent number 8,233,342
- Issue date Jul 31, 2012
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing low power data predicting local evaluation for double...
- Patent number 8,213,249
- Issue date Jul 3, 2012
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed testing of integrated devices
- Patent number 8,108,739
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-body contacted sense amplifier with negligible history effect
- Patent number 7,983,080
- Issue date Jul 19, 2011
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Self clock generation structure for low power local clock buffering...
- Patent number 7,860,172
- Issue date Dec 28, 2010
- International Business Machines Corporation
- Chad Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing enhanced dual mode SRAM performance screen ring oscill...
- Patent number 7,835,176
- Issue date Nov 16, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and computer program for selecting circuit repairs using red...
- Patent number 7,827,018
- Issue date Nov 2, 2010
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Column selectable self-biasing virtual voltages for SRAM write assist
- Patent number 7,817,481
- Issue date Oct 19, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Design structure embodied in a machine readable medium for implemen...
- Patent number 7,788,554
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a random access memory device
- Patent number 7,783,943
- Issue date Aug 24, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for implementing SRAM cell write performance evaluation
- Patent number 7,768,851
- Issue date Aug 3, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Functional float mode screen to test for leakage defects on SRAM bi...
- Patent number 7,760,541
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Chad A Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance read bypass test for SRAM circuits
- Patent number 7,751,266
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing local evaluation of domino read SRAM with enhanced SRA...
- Patent number 7,724,586
- Issue date May 25, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY INTERFACE LATCH WITH INTEGRATED WRITE-THROUGH AND FENCE FUNC...
- Publication number 20190311777
- Publication date Oct 10, 2019
- International Business Machines Corporation
- Elizabeth L. Gerhard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INTERFACE LATCH WITH INTEGRATED WRITE-THROUGH AND FENCE FUNC...
- Publication number 20190164623
- Publication date May 30, 2019
- International Business Machines Corporation
- Elizabeth L. Gerhard
- G11 - INFORMATION STORAGE
Information Patent Application
DEEP SLEEP WAKEUP OF MULTI-BANK MEMORY
- Publication number 20150380065
- Publication date Dec 31, 2015
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTING SENSE AMPLIFIER FOR SENSING LOCAL WRITE DRIVER WITH BO...
- Publication number 20150131368
- Publication date May 14, 2015
- International Business Machines Corporation
- Chad A. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY
- Publication number 20140149818
- Publication date May 29, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY
- Publication number 20140149817
- Publication date May 29, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE
- Publication number 20140112060
- Publication date Apr 24, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE
- Publication number 20140112064
- Publication date Apr 24, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
FINE GRANULARITY POWER GATING
- Publication number 20140092700
- Publication date Apr 3, 2014
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY PULSE WIDTH CONTROL
- Publication number 20140084980
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Chad A. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS
- Publication number 20130286717
- Publication date Oct 31, 2013
- International Business Machines Corporation
- Chad A. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM
- Publication number 20130201753
- Publication date Aug 8, 2013
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTING COLUMN REDUNDANCY STEERING FOR MEMORIES WITH WORDLINE...
- Publication number 20130141986
- Publication date Jun 6, 2013
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Active Bit Line Droop for Read Assist
- Publication number 20120081949
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL SHIFTER FOR USE WITH MEMORY ARRAYS
- Publication number 20120033508
- Publication date Feb 9, 2012
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE...
- Publication number 20110292748
- Publication date Dec 1, 2011
- International Business Machines Corporation
- Chad Allen Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL S...
- Publication number 20110280088
- Publication date Nov 17, 2011
- International Business Machines Corporation
- CHAD A. ADAMS
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Body Contacted Sense Amplifier with Negligible History Effect
- Publication number 20100195408
- Publication date Aug 5, 2010
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscill...
- Publication number 20100188888
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Implementing Variation Tolerant Memory Array Signal Timing
- Publication number 20100118621
- Publication date May 13, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Implementing Local Evaluation of Domino Read SRAM With Enhanced SRA...
- Publication number 20100046278
- Publication date Feb 25, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Functional Float Mode Screen to Test for Leakage Defects on SRAM Bi...
- Publication number 20100039876
- Publication date Feb 18, 2010
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist
- Publication number 20100002495
- Publication date Jan 7, 2010
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
High Performance Read Bypass Test for SRAM Circuits
- Publication number 20090323445
- Publication date Dec 31, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WR...
- Publication number 20090285039
- Publication date Nov 19, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE
- Publication number 20090287971
- Publication date Nov 19, 2009
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
High-Speed Testing of Integrated Devices
- Publication number 20090271669
- Publication date Oct 29, 2009
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDO...
- Publication number 20090235171
- Publication date Sep 17, 2009
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Circuit for Implementing Enhanced SRAM Write and Read Pe...
- Publication number 20090185435
- Publication date Jul 23, 2009
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Computer Program for Selecting Circuit Repairs Using Red...
- Publication number 20090132849
- Publication date May 21, 2009
- Chad A. Adams
- G11 - INFORMATION STORAGE

Chad A. Adams

Person

Patents Grantslast 30 patents

Memory interface latch with integrated write-through and fence func...

Memory interface latch with integrated write-through and fence func...

Memory interface latch with integrated write-through function

Deep sleep wakeup of multi-bank memory

Deep sleep wakeup of multi-bank memory

Fine granularity power gating

Implementing sense amplifier for sensing local write driver with bo...

SRAM global precharge, discharge, and sense

SRAM global precharge, discharge, and sense

Memory array pulse width control

Implementing low power write disabled local evaluation for SRAM

Implementing supply and source write assist for SRAM arrays

Implementing column redundancy steering for memories with wordline...

Active bit line droop for read assist

Single supply sub VDD bit-line precharge SRAM and method for level...

Level shifter for use with memory arrays

Apparatus and method for implementing write assist for static rando...

Implementing low power data predicting local evaluation for double...

High-speed testing of integrated devices

Non-body contacted sense amplifier with negligible history effect

Self clock generation structure for low power local clock buffering...

Implementing enhanced dual mode SRAM performance screen ring oscill...

Method and computer program for selecting circuit repairs using red...

Column selectable self-biasing virtual voltages for SRAM write assist

Design structure embodied in a machine readable medium for implemen...

Method and apparatus for testing a random access memory device

Apparatus for implementing SRAM cell write performance evaluation

Functional float mode screen to test for leakage defects on SRAM bi...

High performance read bypass test for SRAM circuits

Implementing local evaluation of domino read SRAM with enhanced SRA...

Patents Applicationslast 30 patents

MEMORY INTERFACE LATCH WITH INTEGRATED WRITE-THROUGH AND FENCE FUNC...

MEMORY INTERFACE LATCH WITH INTEGRATED WRITE-THROUGH AND FENCE FUNC...

DEEP SLEEP WAKEUP OF MULTI-BANK MEMORY

IMPLEMENTING SENSE AMPLIFIER FOR SENSING LOCAL WRITE DRIVER WITH BO...

DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY

DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY

SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE

SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE

FINE GRANULARITY POWER GATING

MEMORY ARRAY PULSE WIDTH CONTROL

IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS

IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM

IMPLEMENTING COLUMN REDUNDANCY STEERING FOR MEMORIES WITH WORDLINE...

Active Bit Line Droop for Read Assist

LEVEL SHIFTER FOR USE WITH MEMORY ARRAYS

IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE...

SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL S...

Non-Body Contacted Sense Amplifier with Negligible History Effect

Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscill...

Implementing Variation Tolerant Memory Array Signal Timing

Implementing Local Evaluation of Domino Read SRAM With Enhanced SRA...

Functional Float Mode Screen to Test for Leakage Defects on SRAM Bi...

Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist

High Performance Read Bypass Test for SRAM Circuits

METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WR...

METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE

High-Speed Testing of Integrated Devices

APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDO...

Method and Circuit for Implementing Enhanced SRAM Write and Read Pe...

Method and Computer Program for Selecting Circuit Repairs Using Red...