Chang Ho Jung

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Leakage reduction in memory devices
- Patent number 8,780,658
- Issue date Jul 15, 2014
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Address multiplexing in pseudo-dual port memory
- Patent number 8,570,818
- Issue date Oct 29, 2013
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM yield enhancement by read margin improvement
- Patent number 8,208,316
- Issue date Jun 26, 2012
- QUALCOMM Incorporated
- Nan Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timing for a multi-ported memory system
- Patent number 8,082,401
- Issue date Dec 20, 2011
- Qualcomm Incorporated
- Hari Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock and control signal generation for high performance memory dev...
- Patent number 7,881,147
- Issue date Feb 1, 2011
- QUALCOMM Incorporated
- Zhiqin Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Advanced bit line tracking in high performance memory compilers
- Patent number 7,859,920
- Issue date Dec 28, 2010
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Address multiplexing in pseudo-dual port memory
- Patent number 7,760,562
- Issue date Jul 20, 2010
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Semi-shared sense amplifier and global read line architecture
- Patent number 7,656,731
- Issue date Feb 2, 2010
- Qualcomm, Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with delay tracking for improved timing margin
- Patent number 7,646,658
- Issue date Jan 12, 2010
- QUALCOMM Incorporated
- Zhiqin Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-timing circuit with programmable delay and programmable accele...
- Patent number 7,499,347
- Issue date Mar 3, 2009
- QUALCOMM Incorporated
- Zhiqin Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dual port memory having a clock for each port
- Patent number 7,319,632
- Issue date Jan 15, 2008
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dual port memory where ratio of first to second memory acces...
- Patent number 7,251,193
- Issue date Jul 31, 2007
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Self-Timing For A Multi-Ported Memory System
- Publication number 20100250865
- Publication date Sep 30, 2010
- QUALCOMM Incorporated
- Hari Rao
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM Yield Enhancement by Read Margin Improvement
- Publication number 20100046280
- Publication date Feb 25, 2010
- QUALCOMM Incorporated
- Nan Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Address Multiplexing in Pseudo-Dual Port Memory
- Publication number 20090231937
- Publication date Sep 17, 2009
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
Advanced Bit Line Tracking in High Performance Memory Compilers
- Publication number 20090231934
- Publication date Sep 17, 2009
- QUALCOMM Incorporated
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH DELAY TRACKING FOR IMPROVED TIMING MARGIN
- Publication number 20080298143
- Publication date Dec 4, 2008
- Zhiqin Chen
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEV...
- Publication number 20080298142
- Publication date Dec 4, 2008
- Zhiqin Chen
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN MEMORY ARRAYS
- Publication number 20080285367
- Publication date Nov 20, 2008
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE
- Publication number 20080239847
- Publication date Oct 2, 2008
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-TIMING CIRCUIT WITH PROGRAMMABLE DELAY AND PROGRAMMABLE ACCELE...
- Publication number 20080037338
- Publication date Feb 14, 2008
- Zhiqin Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Pseudo-dual port memory where ratio of first to second memory acces...
- Publication number 20070109909
- Publication date May 17, 2007
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
Pseudo-dual port memory having a clock for each port
- Publication number 20070109884
- Publication date May 17, 2007
- Chang Ho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device with row shifting for defective row repair
- Publication number 20060274585
- Publication date Dec 7, 2006
- Chang Ho Jung
- G11 - INFORMATION STORAGE

Chang Ho Jung

Person

Patents Grantslast 30 patents

Leakage reduction in memory devices

Address multiplexing in pseudo-dual port memory

SRAM yield enhancement by read margin improvement

Self-timing for a multi-ported memory system

Clock and control signal generation for high performance memory dev...

Advanced bit line tracking in high performance memory compilers

Address multiplexing in pseudo-dual port memory

Semi-shared sense amplifier and global read line architecture

Memory device with delay tracking for improved timing margin

Self-timing circuit with programmable delay and programmable accele...

Pseudo-dual port memory having a clock for each port

Pseudo-dual port memory where ratio of first to second memory acces...

Patents Applicationslast 30 patents

Self-Timing For A Multi-Ported Memory System

SRAM Yield Enhancement by Read Margin Improvement

Address Multiplexing in Pseudo-Dual Port Memory

Advanced Bit Line Tracking in High Performance Memory Compilers

MEMORY DEVICE WITH DELAY TRACKING FOR IMPROVED TIMING MARGIN

CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEV...

METHOD AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN MEMORY ARRAYS

SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE

SELF-TIMING CIRCUIT WITH PROGRAMMABLE DELAY AND PROGRAMMABLE ACCELE...

Pseudo-dual port memory where ratio of first to second memory acces...

Pseudo-dual port memory having a clock for each port

Memory device with row shifting for defective row repair