Chanh Tran

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Distributed on-chip decoupling apparatus and method using package i...
- Patent number 9,870,982
- Issue date Jan 16, 2018
- Rambus Inc.
- David Secker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distributed on-chip decoupling apparatus and method using package i...
- Patent number 9,466,568
- Issue date Oct 11, 2016
- Rambus Inc.
- David Secker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed on-chip decoupling apparatus and method using package i...
- Patent number 9,006,907
- Issue date Apr 14, 2015
- Rambus Inc.
- David Secker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 8,458,426
- Issue date Jun 4, 2013
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-test method for interface circuit
- Patent number 8,378,699
- Issue date Feb 19, 2013
- Rambus Inc.
- Bret Stott
- G11 - INFORMATION STORAGE
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 8,086,812
- Issue date Dec 27, 2011
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface test circuit
- Patent number 7,535,242
- Issue date May 19, 2009
- Rambus Inc.
- Bret Stott
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop circuitry for clock delay adjustment
- Patent number 7,308,065
- Issue date Dec 11, 2007
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 7,124,270
- Issue date Oct 17, 2006
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive impedance output driver circuit
- Patent number 7,088,127
- Issue date Aug 8, 2006
- Rambus, Inc.
- Huy M. Ngyuen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 7,065,622
- Issue date Jun 20, 2006
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop circuitry for clock delay adjustment
- Patent number 7,039,147
- Issue date May 2, 2006
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 7,010,658
- Issue date Mar 7, 2006
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for voltage level shifting in input circuitry
- Patent number 6,819,137
- Issue date Nov 16, 2004
- Rambus Inc.
- Yueyong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit, apparatus and method having a cross-coupled load with curr...
- Patent number 6,809,569
- Issue date Oct 26, 2004
- Rambus Inc.
- Yueyong Wang
- G05 - CONTROLLING REGULATING
Information Patent Grant
Circuit, apparatus and method for an adaptive voltage swing limiter
- Patent number 6,803,823
- Issue date Oct 12, 2004
- Rambus Inc.
- Yueyong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 6,643,752
- Issue date Nov 4, 2003
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop circuitry for clock delay adjustment
- Patent number 6,539,072
- Issue date Mar 25, 2003
- Rambus, Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay-locked loop circuitry for clock delay adjustment
- Patent number 6,125,157
- Issue date Sep 26, 2000
- Rambus, Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus driver circuit including a slew rate indicator circuit having a...
- Patent number 5,959,481
- Issue date Sep 28, 1999
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE I...
- Publication number 20170098595
- Publication date Apr 6, 2017
- RAMBUS INC.
- David Secker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE I...
- Publication number 20150221589
- Publication date Aug 6, 2015
- RAMBUS INC.
- David Secker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE I...
- Publication number 20130320560
- Publication date Dec 5, 2013
- RAMBUS INC.
- David Secker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-Test Method for Interface Circuit
- Publication number 20090206867
- Publication date Aug 20, 2009
- Bret Stott
- G01 - MEASURING TESTING
Information Patent Application
Interface test circuit
- Publication number 20070257693
- Publication date Nov 8, 2007
- Bret Stott
- G01 - MEASURING TESTING
Information Patent Application
TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
- Publication number 20070118711
- Publication date May 24, 2007
- RAMBUS INC.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
- Publication number 20070011426
- Publication date Jan 11, 2007
- RAMBUS INC.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay locked loop circuitry for clock delay adjustment
- Publication number 20060188051
- Publication date Aug 24, 2006
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transceiver with latency alignment circuitry
- Publication number 20050160247
- Publication date Jul 21, 2005
- John B. Dillon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transceiver with latency alignment circuitry
- Publication number 20050149685
- Publication date Jul 7, 2005
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE IMPEDANCE OUTPUT DRIVER CIRCUIT
- Publication number 20050057275
- Publication date Mar 17, 2005
- Huy M. Ngyuen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop circuitry for clock delay adjustment
- Publication number 20040223571
- Publication date Nov 11, 2004
- Rambus Inc.
- Kevin S. Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transceiver with latency alignment circuitry
- Publication number 20040128460
- Publication date Jul 1, 2004
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit, apparatus and method for an adaptive voltage swing limiter
- Publication number 20040000955
- Publication date Jan 1, 2004
- Yueyong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit, apparatus and method having a cross-coupled load with curr...
- Publication number 20030160642
- Publication date Aug 28, 2003
- Yueyong Wang
- G05 - CONTROLLING REGULATING

Person

Patents Grantslast 30 patents

Distributed on-chip decoupling apparatus and method using package i...

Distributed on-chip decoupling apparatus and method using package i...

Distributed on-chip decoupling apparatus and method using package i...

Transceiver with latency alignment circuitry

Self-test method for interface circuit

Transceiver with latency alignment circuitry

Interface test circuit

Delay locked loop circuitry for clock delay adjustment

Transceiver with latency alignment circuitry

Adaptive impedance output driver circuit

Transceiver with latency alignment circuitry

Delay locked loop circuitry for clock delay adjustment

Transceiver with latency alignment circuitry

Technique for voltage level shifting in input circuitry

Circuit, apparatus and method having a cross-coupled load with curr...

Circuit, apparatus and method for an adaptive voltage swing limiter

Transceiver with latency alignment circuitry

Delay locked loop circuitry for clock delay adjustment

Delay-locked loop circuitry for clock delay adjustment

Bus driver circuit including a slew rate indicator circuit having a...

Patents Applicationslast 30 patents

DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE I...

DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE I...

DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE I...

Self-Test Method for Interface Circuit

Interface test circuit

TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY

TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY

Delay locked loop circuitry for clock delay adjustment

Transceiver with latency alignment circuitry

Transceiver with latency alignment circuitry

ADAPTIVE IMPEDANCE OUTPUT DRIVER CIRCUIT

Delay locked loop circuitry for clock delay adjustment

Transceiver with latency alignment circuitry

Circuit, apparatus and method for an adaptive voltage swing limiter

Circuit, apparatus and method having a cross-coupled load with curr...