Charles E. May

Person

Gresham, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Arrangement and method for fabricating a semiconductor wafer
- Patent number 7,601,643
- Issue date Oct 13, 2009
- LSI Logic Corporation
- Charles E. May
- B24 - GRINDING POLISHING
Information Patent Grant
Method for redirecting void diffusion away from vias in an integrat...
- Patent number 7,582,566
- Issue date Sep 1, 2009
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for diverting void diffusion in integrated cir...
- Patent number 7,436,040
- Issue date Oct 14, 2008
- LSI Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for redirecting void diffusion away from vias...
- Patent number 7,361,965
- Issue date Apr 22, 2008
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a low k polymer E-beam printable mechanical support
- Patent number 7,358,594
- Issue date Apr 15, 2008
- LSI Logic Corporation
- Derryl J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bond pad design
- Patent number 7,023,067
- Issue date Apr 4, 2006
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low k polymer E-beam printable mechanical support
- Patent number 6,972,217
- Issue date Dec 6, 2005
- LSI Logic Corporation
- Derryl J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Temperature control system
- Patent number 6,967,177
- Issue date Nov 22, 2005
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via and metal line interface capable of reducing the incidence of e...
- Patent number 6,875,693
- Issue date Apr 5, 2005
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance MOSFET with modulated channel gate thickness
- Patent number 6,743,688
- Issue date Jun 1, 2004
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer arrangement of a semiconductor wafer
- Patent number 6,707,114
- Issue date Mar 16, 2004
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal low k dielectrics
- Patent number 6,654,226
- Issue date Nov 25, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal characterization compensation
- Patent number 6,638,776
- Issue date Oct 28, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ion beam dual damascene process
- Patent number 6,620,729
- Issue date Sep 16, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for improving mechanical strength of layers of low k dielec...
- Patent number 6,566,244
- Issue date May 20, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of contamination-free manufacturing data in fault detection and...
- Patent number 6,560,504
- Issue date May 6, 2003
- Advanced Micro Devices, Inc.
- Thomas J. Goodwin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Polysilicon gate salicidation
- Patent number 6,544,829
- Issue date Apr 8, 2003
- LSI Logic Corporation
- Venkatesh Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced fabrication technique to form ultra thin gate dielectric u...
- Patent number 6,531,364
- Issue date Mar 11, 2003
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer arrangement and method of processing a semicond...
- Patent number 6,521,520
- Issue date Feb 18, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable read only memory in CMOS process flow
- Patent number 6,495,881
- Issue date Dec 17, 2002
- LSI Logic Corporation
- Shafqat Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarizing an isolation structure in a substrate
- Patent number 6,482,075
- Issue date Nov 19, 2002
- LSI Logic Corporation
- Hemanshu D. Bhatt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Drop-in test structure and methodology for characterizing an integr...
- Patent number 6,452,412
- Issue date Sep 17, 2002
- Advanced Micro Devices, Inc.
- Richard W. Jarvis
- G01 - MEASURING TESTING
Information Patent Grant
Transistor with an ultra short channel length defined by a laterall...
- Patent number 6,451,657
- Issue date Sep 17, 2002
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of coupling capacitance reduction
- Patent number 6,432,812
- Issue date Aug 13, 2002
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming electrode for high performance semiconductor devices
- Patent number 6,420,220
- Issue date Jul 16, 2002
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor having enhanced metal silicide and a self-aligned gate e...
- Patent number 6,410,967
- Issue date Jun 25, 2002
- Advanced Micro Devices, Inc.
- Frederick N. Hause
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced trench isolation structure
- Patent number 6,403,445
- Issue date Jun 11, 2002
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor topography having improved active device isolation an...
- Patent number 6,362,510
- Issue date Mar 26, 2002
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High pressure N2 RTA process for TiS2 formation
- Patent number 6,348,413
- Issue date Feb 19, 2002
- Advanced Micro Devices, Inc.
- Timothy Z. Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable read only memory in CMOS process flow
- Patent number 6,338,992
- Issue date Jan 15, 2002
- LSI Logic Corporation
- Shafqat Ahmed
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRAT...
- Publication number 20080132065
- Publication date Jun 5, 2008
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for diverting void diffusion in integrated cir...
- Publication number 20070259518
- Publication date Nov 8, 2007
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for redirecting void diffusion away from vias...
- Publication number 20070155160
- Publication date Jul 5, 2007
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Extreme low-K interconnect structure and method
- Publication number 20060006538
- Publication date Jan 12, 2006
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Temperature control system
- Publication number 20050279284
- Publication date Dec 22, 2005
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via and metal line interface capable of reducing the incidence of e...
- Publication number 20050064708
- Publication date Mar 24, 2005
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ion implantation phase shift mask
- Publication number 20040241554
- Publication date Dec 2, 2004
- LSI Logic Corporation, Milpitas, CA
- Paul Rissman
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Bond pad design
- Publication number 20040135223
- Publication date Jul 15, 2004
- Derryl D.J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ion beam dual damascene process
- Publication number 20030203620
- Publication date Oct 30, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermal low k dielectrics
- Publication number 20030170973
- Publication date Sep 11, 2003
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermal characterization compensation
- Publication number 20030157735
- Publication date Aug 21, 2003
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Coupling capacitance reduction
- Publication number 20030013298
- Publication date Jan 16, 2003
- LSI Logic Corporation
- Charles E. May
- H01 - BASIC ELECTRIC ELEMENTS

Charles E. May

Person

Patents Grantslast 30 patents

Arrangement and method for fabricating a semiconductor wafer

Method for redirecting void diffusion away from vias in an integrat...

Method and apparatus for diverting void diffusion in integrated cir...

Method and apparatus for redirecting void diffusion away from vias...

Method of forming a low k polymer E-beam printable mechanical support

Bond pad design

Low k polymer E-beam printable mechanical support

Temperature control system

Via and metal line interface capable of reducing the incidence of e...

High performance MOSFET with modulated channel gate thickness

Semiconductor wafer arrangement of a semiconductor wafer

Thermal low k dielectrics

Thermal characterization compensation

Ion beam dual damascene process

Process for improving mechanical strength of layers of low k dielec...

Use of contamination-free manufacturing data in fault detection and...

Polysilicon gate salicidation

Advanced fabrication technique to form ultra thin gate dielectric u...

Semiconductor wafer arrangement and method of processing a semicond...

Programmable read only memory in CMOS process flow

Process for planarizing an isolation structure in a substrate

Drop-in test structure and methodology for characterizing an integr...

Transistor with an ultra short channel length defined by a laterall...

Method of coupling capacitance reduction

Method of forming electrode for high performance semiconductor devices

Transistor having enhanced metal silicide and a self-aligned gate e...

Enhanced trench isolation structure

Semiconductor topography having improved active device isolation an...

High pressure N2 RTA process for TiS2 formation

Programmable read only memory in CMOS process flow

Patents Applicationslast 30 patents

METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRAT...

Method and apparatus for diverting void diffusion in integrated cir...

Method and apparatus for redirecting void diffusion away from vias...

Extreme low-K interconnect structure and method

Temperature control system

Via and metal line interface capable of reducing the incidence of e...

Ion implantation phase shift mask

Bond pad design

Ion beam dual damascene process

Thermal low k dielectrics

Thermal characterization compensation

Coupling capacitance reduction