Cheang-Whang Chang

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit (IC) structure protection scheme
- Patent number 12,068,257
- Issue date Aug 20, 2024
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single event upset tolerant memory device
- Patent number 12,045,469
- Issue date Jul 23, 2024
- Xilinx, Inc.
- Kumar Rahul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interwafer connection structure for coupling wafers in a wafer stack
- Patent number 11,901,338
- Issue date Feb 13, 2024
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Runtime measurement of process variations and supply voltage charac...
- Patent number 11,585,854
- Issue date Feb 21, 2023
- Xilinx, Inc.
- Da Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked silicon package assembly having vertical thermal management
- Patent number 11,488,936
- Issue date Nov 1, 2022
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management
- Patent number 11,355,412
- Issue date Jun 7, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with stacked dies having mirrored circuitry
- Patent number 11,205,639
- Issue date Dec 21, 2021
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management
- Patent number 11,145,566
- Issue date Oct 12, 2021
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC die with dummy structures
- Patent number 11,114,344
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Hui-Wen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuits for testing a die stack
- Patent number 11,054,461
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Nui Chong
- G01 - MEASURING TESTING
Information Patent Grant
Package integration for memory devices
- Patent number 10,770,430
- Issue date Sep 8, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with modular core dice
- Patent number 10,692,837
- Issue date Jun 23, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer edge partial die engineered for stacked die yield
- Patent number 10,431,565
- Issue date Oct 1, 2019
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-die transistor characterization in an IC
- Patent number 10,379,155
- Issue date Aug 13, 2019
- Xilinx, Inc.
- Ping-Chin Yeh
- G01 - MEASURING TESTING
Information Patent Grant
Circuit for and method of testing bond connections between a first...
- Patent number 10,262,911
- Issue date Apr 16, 2019
- Xilinx, Inc.
- Yuqing Gong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and design of low sheet resistance MEOL resistors
- Patent number 10,103,139
- Issue date Oct 16, 2018
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for assembling and testing a multi-integrated...
- Patent number 10,096,502
- Issue date Oct 9, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shielded wire arrangement for die testing
- Patent number 9,412,674
- Issue date Aug 9, 2016
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of testing a semiconductor structure
- Patent number 8,810,269
- Issue date Aug 19, 2014
- Xilinx, Inc.
- Yuqing Gong
- G01 - MEASURING TESTING
Information Patent Grant
Methods of manufacturing a semiconductor structure
- Patent number 8,802,454
- Issue date Aug 12, 2014
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE ASSEMBLY WITH ENHANCED SOLDER PITCH
- Publication number 20240321793
- Publication date Sep 26, 2024
- Xilinx, Inc.
- Yun WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE EVENT UPSET TOLERANT MEMORY DEVICE
- Publication number 20240201863
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Kumar RAHUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT (IC) Protections
- Publication number 20240145411
- Publication date May 2, 2024
- Xilinx, Inc.
- Myongseob KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MITIGATING WARPAGE ON STACKED WAFERS
- Publication number 20240038556
- Publication date Feb 1, 2024
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACK
- Publication number 20230140675
- Publication date May 4, 2023
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STACKED DIES HAVING MIRRORED CIRCUITRY
- Publication number 20210265312
- Publication date Aug 26, 2021
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT
- Publication number 20210249328
- Publication date Aug 12, 2021
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT
- Publication number 20210193620
- Publication date Jun 24, 2021
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE INTEGRATION FOR MEMORY DEVICES
- Publication number 20200303341
- Publication date Sep 24, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT
- Publication number 20200105642
- Publication date Apr 2, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR ASSEMBLING AND TESTING A MULTI-INTEGRATED...
- Publication number 20180144963
- Publication date May 24, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS
- Publication number 20170012041
- Publication date Jan 12, 2017
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC
- Publication number 20160097805
- Publication date Apr 7, 2016
- Xilinx, Inc.
- Ping-Chin Yeh
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF TESTING A SEMICONDUCTOR STRUCTURE
- Publication number 20140091819
- Publication date Apr 3, 2014
- Xilinx, Inc.
- Yuqing Gong
- G01 - MEASURING TESTING

Cheang-Whang Chang

Person

Patents Grantslast 30 patents

Integrated circuit (IC) structure protection scheme

Single event upset tolerant memory device

Interwafer connection structure for coupling wafers in a wafer stack

Runtime measurement of process variations and supply voltage charac...

Stacked silicon package assembly having vertical thermal management

Stacked silicon package assembly having thermal management

Integrated circuit device with stacked dies having mirrored circuitry

Stacked silicon package assembly having thermal management

IC die with dummy structures

Test circuits for testing a die stack

Package integration for memory devices

Chip package assembly with modular core dice

Wafer edge partial die engineered for stacked die yield

In-die transistor characterization in an IC

Circuit for and method of testing bond connections between a first...

Method and design of low sheet resistance MEOL resistors

Method and apparatus for assembling and testing a multi-integrated...

Shielded wire arrangement for die testing

Method of testing a semiconductor structure

Methods of manufacturing a semiconductor structure

Patents Applicationslast 30 patents

CHIP PACKAGE ASSEMBLY WITH ENHANCED SOLDER PITCH

SINGLE EVENT UPSET TOLERANT MEMORY DEVICE

INTEGRATED CIRCUIT (IC) Protections

METHOD FOR MITIGATING WARPAGE ON STACKED WAFERS

INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACK

INTEGRATED CIRCUIT DEVICE WITH STACKED DIES HAVING MIRRORED CIRCUITRY

STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT

STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT

PACKAGE INTEGRATION FOR MEMORY DEVICES

STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT

METHOD AND APPARATUS FOR ASSEMBLING AND TESTING A MULTI-INTEGRATED...

METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS

IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC

METHOD OF TESTING A SEMICONDUCTOR STRUCTURE