Chee Bow Lim

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chassis interconnect for an electronic device
- Patent number 11,445,608
- Issue date Sep 13, 2022
- Intel Corporation
- Chee How Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System to calibrate on-die temperature sensor
- Patent number 7,695,189
- Issue date Apr 13, 2010
- Intel Corporation
- Chee H. Lim
- G01 - MEASURING TESTING
Information Patent Grant
System to calibrate on-die temperature sensor
- Patent number 7,417,448
- Issue date Aug 26, 2008
- Intel Corporation
- Chee H. Lim
- G01 - MEASURING TESTING
Information Patent Grant
Digital frequency synthesis clocked circuits
- Patent number 7,257,756
- Issue date Aug 14, 2007
- Intel Corporation
- Neal Wolff
- G01 - MEASURING TESTING
Information Patent Grant
Phase locked loop system capable of deskewing
- Patent number 7,199,624
- Issue date Apr 3, 2007
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global I/O timing adjustment using calibrated delay elements
- Patent number 7,197,659
- Issue date Mar 27, 2007
- Intel Corporation
- Chee How Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-loop circuit capable of providing a delayed clock in phase lo...
- Patent number 7,184,503
- Issue date Feb 27, 2007
- Intel Corporation
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for utilization of asymmetric secondary processing resou...
- Patent number 7,100,060
- Issue date Aug 29, 2006
- Intel Corporation
- Zhong-Ning Cai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for jitter reduction in phase locked loops
- Patent number 7,023,945
- Issue date Apr 4, 2006
- Intel Corporation
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing lock time in dual charge-pump pha...
- Patent number 6,937,075
- Issue date Aug 30, 2005
- Intel Corporation
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage ID based frequency control for clock generating circuit
- Patent number 6,924,710
- Issue date Aug 2, 2005
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for fast lock acquisition in self-biased phase...
- Patent number 6,919,769
- Issue date Jul 19, 2005
- Intel Corporation
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascaded phase-locked loops
- Patent number 6,842,056
- Issue date Jan 11, 2005
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage ID based frequency control for clock generating circuit
- Patent number 6,809,606
- Issue date Oct 26, 2004
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency control for clock generating circuit
- Patent number 6,771,134
- Issue date Aug 3, 2004
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to provide a single reference component for mu...
- Patent number 6,756,810
- Issue date Jun 29, 2004
- Intel Corporation
- Usman A. Mughal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clocking an I/O buffer, having a selectable phase difference from t...
- Patent number 6,748,549
- Issue date Jun 8, 2004
- Intel Corporation
- Chi-Yeu Chao
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method to use a single reference component in a maste...
- Patent number 6,717,455
- Issue date Apr 6, 2004
- Intel Corporation
- Usman A. Mughal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable lock window for a phase locked loop
- Patent number 6,614,317
- Issue date Sep 2, 2003
- Intel Corporation
- Keng L. Wong
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Apparatus and method to provide a single reference component for mu...
- Patent number 6,545,522
- Issue date Apr 8, 2003
- Intel Corporation
- Usman A. Mughal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method to use a single reference component in a maste...
- Patent number 6,535,047
- Issue date Mar 18, 2003
- Intel Corporation
- Usman A. Mughal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bus termination scheme for flexible uni-processor and dual processo...
- Patent number 6,522,165
- Issue date Feb 18, 2003
- Intel Corporation
- Vijayalakshmi Ramachandran
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit compensation technique
- Patent number 6,509,780
- Issue date Jan 21, 2003
- Intel Corp.
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for linear on-die termination in an open drain...
- Patent number 6,424,170
- Issue date Jul 23, 2002
- Intel Corporation
- Raghu P. Raman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for dynamic on-die termination in an open-drai...
- Patent number 6,411,122
- Issue date Jun 25, 2002
- Intel Corporation
- Usman A. Mughal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Passive voltage limiter
- Patent number 6,351,136
- Issue date Feb 26, 2002
- Intel Corporation
- Jeff R. Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-die adaptive arrangements for continuous process, voltage and te...
- Patent number 6,326,802
- Issue date Dec 4, 2001
- Intel Corporation
- Paul F. Newman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-chip termination
- Patent number 6,157,206
- Issue date Dec 5, 2000
- Intel Corporation
- Gregory F. Taylor
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CHASSIS INTERCONNECT FOR AN ELECTRONIC DEVICE
- Publication number 20210100101
- Publication date Apr 1, 2021
- Intel Corporation
- Chee How Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM TO CALIBRATE ON-DIE TEMPERATURE SENSOR
- Publication number 20080304546
- Publication date Dec 11, 2008
- Chee H. Lim
- G01 - MEASURING TESTING
Information Patent Application
System to calibrate on-die temperature sensor
- Publication number 20080001615
- Publication date Jan 3, 2008
- Chee H. Lim
- G01 - MEASURING TESTING
Information Patent Application
Phase interpolation for phase-locked loops
- Publication number 20070153951
- Publication date Jul 5, 2007
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low-jitter clock distribution
- Publication number 20070120588
- Publication date May 31, 2007
- Chee How Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techiniques for utilization of asymmetric secondary processing reso...
- Publication number 20060288244
- Publication date Dec 21, 2006
- Zhong-Ning Cai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for jitter reduction in phase locked loops
- Publication number 20060091964
- Publication date May 4, 2006
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital frequency synthesis clocked circuits
- Publication number 20050229066
- Publication date Oct 13, 2005
- Neal Wolff
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for fast lock acquisition in self-biased phase...
- Publication number 20050062548
- Publication date Mar 24, 2005
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CASCADED PHASE-LOCKED LOOPS
- Publication number 20040263223
- Publication date Dec 30, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing lock time in dual charge-pump pha...
- Publication number 20040239386
- Publication date Dec 2, 2004
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase locked loop system capable of deskewing
- Publication number 20040217787
- Publication date Nov 4, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage ID based frequency control for clock generating circuit
- Publication number 20040080347
- Publication date Apr 29, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for utilization of asymmetric secondary processing resou...
- Publication number 20040003309
- Publication date Jan 1, 2004
- Zhong-Ning Cai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for jitter reduction in phase locked loops
- Publication number 20030231730
- Publication date Dec 18, 2003
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage ID based frequency control for clock generating circuit
- Publication number 20030206071
- Publication date Nov 6, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequency control for clock generating circuit
- Publication number 20030206068
- Publication date Nov 6, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to provide a single reference component for mu...
- Publication number 20030112050
- Publication date Jun 19, 2003
- Usman A. Mughal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and method of use a single reference component in a maste...
- Publication number 20030094991
- Publication date May 22, 2003
- Usman A. Mughal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Global I/O timing adjustment using calibrated delay elements
- Publication number 20030065962
- Publication date Apr 3, 2003
- Chee How Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS TERMINATION SCHEME FOR FLEXIBLE UNI-PROCESSOR AND DUAL PROCESSO...
- Publication number 20030001610
- Publication date Jan 2, 2003
- Vijayalakshmi Ramachandran
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Variable lock window for a phase locked loop
- Publication number 20020175769
- Publication date Nov 28, 2002
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method to provide a single reference component for mu...
- Publication number 20020172066
- Publication date Nov 21, 2002
- Usman A. Mughal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and method to use a single reference component in a maste...
- Publication number 20020171466
- Publication date Nov 21, 2002
- Usman A. Mughal
- H03 - BASIC ELECTRONIC CIRCUITRY

Chee Bow Lim

Person

Patents Grantslast 30 patents

Chassis interconnect for an electronic device

System to calibrate on-die temperature sensor

System to calibrate on-die temperature sensor

Digital frequency synthesis clocked circuits

Phase locked loop system capable of deskewing

Global I/O timing adjustment using calibrated delay elements

Multi-loop circuit capable of providing a delayed clock in phase lo...

Techniques for utilization of asymmetric secondary processing resou...

Method and apparatus for jitter reduction in phase locked loops

Method and apparatus for reducing lock time in dual charge-pump pha...

Voltage ID based frequency control for clock generating circuit

Method and apparatus for fast lock acquisition in self-biased phase...

Cascaded phase-locked loops

Voltage ID based frequency control for clock generating circuit

Frequency control for clock generating circuit

Apparatus and method to provide a single reference component for mu...

Clocking an I/O buffer, having a selectable phase difference from t...

Apparatus and method to use a single reference component in a maste...

Variable lock window for a phase locked loop

Apparatus and method to provide a single reference component for mu...

Apparatus and method to use a single reference component in a maste...

Bus termination scheme for flexible uni-processor and dual processo...

Circuit compensation technique

Apparatus and method for linear on-die termination in an open drain...

Apparatus and method for dynamic on-die termination in an open-drai...

Passive voltage limiter

On-die adaptive arrangements for continuous process, voltage and te...

On-chip termination

Patents Applicationslast 30 patents

CHASSIS INTERCONNECT FOR AN ELECTRONIC DEVICE

SYSTEM TO CALIBRATE ON-DIE TEMPERATURE SENSOR

System to calibrate on-die temperature sensor

Phase interpolation for phase-locked loops

Low-jitter clock distribution

Techiniques for utilization of asymmetric secondary processing reso...

Method and apparatus for jitter reduction in phase locked loops

Digital frequency synthesis clocked circuits

Method and apparatus for fast lock acquisition in self-biased phase...

CASCADED PHASE-LOCKED LOOPS

Method and apparatus for reducing lock time in dual charge-pump pha...

Phase locked loop system capable of deskewing

Voltage ID based frequency control for clock generating circuit

Techniques for utilization of asymmetric secondary processing resou...

Method and apparatus for jitter reduction in phase locked loops

Voltage ID based frequency control for clock generating circuit

Frequency control for clock generating circuit

Apparatus and method to provide a single reference component for mu...

Apparatus and method of use a single reference component in a maste...

Global I/O timing adjustment using calibrated delay elements

BUS TERMINATION SCHEME FOR FLEXIBLE UNI-PROCESSOR AND DUAL PROCESSO...

Variable lock window for a phase locked loop

Apparatus and method to provide a single reference component for mu...

Apparatus and method to use a single reference component in a maste...