Chee Keong Chin

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Aperture structure on semiconductor component backside to alleviate...
- Patent number 11,289,395
- Issue date Mar 29, 2022
- Western Digital Technologies, Inc.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with top die positioned to reduce die cracking
- Patent number 11,177,241
- Issue date Nov 16, 2021
- Western Digital Technologies, Inc.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including dual pad wire bond interconnection
- Patent number 10,483,239
- Issue date Nov 19, 2019
- SanDisk Semiconductor (Shanghai) Co. Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including corner recess
- Patent number 10,418,334
- Issue date Sep 17, 2019
- SanDisk Semiconductor (Shanghai) Co. Ltd.
- Hang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including conductive bump interconnections
- Patent number 10,283,485
- Issue date May 7, 2019
- SanDisk Semiconductor (Shanghai) Co. Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including die bond pads at a die edge
- Patent number 10,128,218
- Issue date Nov 13, 2018
- SanDisk Semiconductor (Shanghai) Co. Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package-in-package system housing a plurality of...
- Patent number 8,946,878
- Issue date Feb 3, 2015
- Stats Chippac Ltd.
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device system with stacked packages
- Patent number 8,288,860
- Issue date Oct 16, 2012
- Stats Chippac Ltd.
- Chee Keong Chin
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit package system with offset stacked die and metho...
- Patent number 8,242,607
- Issue date Aug 14, 2012
- Stats Chippac Ltd.
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pick-up heads and systems for die bonding and related applications
- Patent number 8,037,918
- Issue date Oct 18, 2011
- Stats Chippac, Inc.
- Ya Ping Wang
- B32 - LAYERED PRODUCTS
Information Patent Grant
Integrated circuit package system with support structure for die ov...
- Patent number 7,989,941
- Issue date Aug 2, 2011
- Stats Chippac Ltd.
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Wafer Dicing Method
- Publication number 20230402323
- Publication date Dec 14, 2023
- Western Digital Technologies, Inc.
- Zhengjie ZHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH REDUCED STRESS DIE PICK AND PLACE
- Publication number 20220181208
- Publication date Jun 9, 2022
- Western Digital Technologies, Inc.
- Xin Tian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH TOP DIE POSITIONED TO REDUCE DIE CRACKING
- Publication number 20200381401
- Publication date Dec 3, 2020
- Western Digital Technologies, Inc.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APERTURE STRUCTURE ON SEMICONDUCTOR COMPONENT BACKSIDE TO ALLEVIATE...
- Publication number 20200335481
- Publication date Oct 22, 2020
- Western Digital Technologies, Inc.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE BUMP INTERCONNECTIONS
- Publication number 20180337161
- Publication date Nov 22, 2018
- Sandisk Semiconductor (Shanghai) Co., Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION
- Publication number 20180190621
- Publication date Jul 5, 2018
- Sandisk Semiconductor (Shanghai) Co., Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING CORNER RECESS
- Publication number 20180174983
- Publication date Jun 21, 2018
- Sandisk Semiconductor (Shanghai) Co., Ltd.
- Hang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING DIE BOND PADS AT A DIE EDGE
- Publication number 20180175006
- Publication date Jun 21, 2018
- Sandisk Semiconductor (Shanghai) Co., Ltd.
- Junrong Yan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE FOR DIE OV...
- Publication number 20090236751
- Publication date Sep 24, 2009
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
- Publication number 20090146271
- Publication date Jun 11, 2009
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE SYSTEM WITH STACKED PACKAGES
- Publication number 20090072378
- Publication date Mar 19, 2009
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER TRANSPORT SYSTEM
- Publication number 20080237157
- Publication date Oct 2, 2008
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
- Publication number 20080150158
- Publication date Jun 26, 2008
- Chee Keong Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pick-up heads and systems for die bonding and related applications
- Publication number 20080128081
- Publication date Jun 5, 2008
- STATS ChipPAC, Inc.
- Ya Ping Wang
- B32 - LAYERED PRODUCTS
Information Patent Application
SAWN INTEGRATED CIRCUIT PACKAGE SYSTEM
- Publication number 20070284139
- Publication date Dec 13, 2007
- Chee Keong Chin
- B28 - WORKING CEMENT, CLAY, OR STONE

Chee Keong Chin

Person

Patents Grantslast 30 patents

Aperture structure on semiconductor component backside to alleviate...

Semiconductor device with top die positioned to reduce die cracking

Semiconductor device including dual pad wire bond interconnection

Semiconductor device including corner recess

Semiconductor device including conductive bump interconnections

Semiconductor device including die bond pads at a die edge

Integrated circuit package-in-package system housing a plurality of...

Memory device system with stacked packages

Integrated circuit package system with offset stacked die and metho...

Pick-up heads and systems for die bonding and related applications

Integrated circuit package system with support structure for die ov...

Patents Applicationslast 30 patents

Semiconductor Wafer Dicing Method

SEMICONDUCTOR DEVICE WITH REDUCED STRESS DIE PICK AND PLACE

SEMICONDUCTOR DEVICE WITH TOP DIE POSITIONED TO REDUCE DIE CRACKING

APERTURE STRUCTURE ON SEMICONDUCTOR COMPONENT BACKSIDE TO ALLEVIATE...

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE BUMP INTERCONNECTIONS

SEMICONDUCTOR DEVICE INCLUDING DUAL PAD WIRE BOND INTERCONNECTION

SEMICONDUCTOR DEVICE INCLUDING CORNER RECESS

SEMICONDUCTOR DEVICE INCLUDING DIE BOND PADS AT A DIE EDGE

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE FOR DIE OV...

INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM

MEMORY DEVICE SYSTEM WITH STACKED PACKAGES

WAFER TRANSPORT SYSTEM

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE

Pick-up heads and systems for die bonding and related applications

SAWN INTEGRATED CIRCUIT PACKAGE SYSTEM