Cheemen Yu

Person

Madison, WI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Printed circuit board with coextensive electrical connectors and co...
- Patent number 9,006,912
- Issue date Apr 14, 2015
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Molded SiP package with reinforced solder columns
- Patent number 8,878,346
- Issue date Nov 4, 2014
- SanDisk Technologies Inc.
- Chin-Tien Chiu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of fabricating a memory card using SIP/SMT hybrid technology
- Patent number 8,728,864
- Issue date May 20, 2014
- SanDisk Technologies Inc.
- Ning Ye
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Two-sided substrate lead connection for minimizing kerf width on a...
- Patent number 8,637,972
- Issue date Jan 28, 2014
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rigid wave pattern design on chip carrier substrate and printed cir...
- Patent number 8,487,441
- Issue date Jul 16, 2013
- SanDisk Technologies Inc.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating stacked semiconductor package with localized...
- Patent number 8,470,640
- Issue date Jun 25, 2013
- SanDisk Technologies Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-sided die in a four-sided leadframe based package
- Patent number 8,395,246
- Issue date Mar 12, 2013
- SanDisk Technologies Inc.
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a memory card using SiP/SMT hybrid technology
- Patent number 8,318,535
- Issue date Nov 27, 2012
- SanDisk Technologies Inc.
- Ning Ye
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Stacked semiconductor package with localized cavities for wire bonding
- Patent number 8,294,251
- Issue date Oct 23, 2012
- SanDisk Technologies Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die having a redistribution layer
- Patent number 8,212,360
- Issue date Jul 3, 2012
- SanDisk Technologies Inc.
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die package with asymmetric leadframe connection
- Patent number 8,097,495
- Issue date Jan 17, 2012
- SanDisk Technologies Inc.
- Ming Hsun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a two-sided die in a four-sided leadframe bas...
- Patent number 8,058,099
- Issue date Nov 15, 2011
- SanDisk Technologies Inc.
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Padless substrate for surface mounted components
- Patent number 7,967,184
- Issue date Jun 28, 2011
- SanDisk Corporation
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package having through holes for molding back side of...
- Patent number 7,952,179
- Issue date May 31, 2011
- SanDisk Corporation
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a semiconductor package having through holes...
- Patent number 7,939,382
- Issue date May 10, 2011
- SanDisk Corporation
- Chin-Tien Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rounded contact fingers on substrate/PCB for crack prevention
- Patent number 7,806,731
- Issue date Oct 5, 2010
- SanDisk Corporation
- Hem Takiar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of forming a single layer substrate for high capacity memor...
- Patent number 7,772,107
- Issue date Aug 10, 2010
- SanDisk Corporation
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory card fabricated using SiP/SMT hybrid technology
- Patent number 7,772,686
- Issue date Aug 10, 2010
- SanDisk Corporation
- Ning Ye
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of fabricating a semiconductor die having a redistribution l...
- Patent number 7,772,047
- Issue date Aug 10, 2010
- SanDisk Corporation
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die having a distribution layer
- Patent number 7,763,980
- Issue date Jul 27, 2010
- SanDisk Corporation
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board with coextensive electrical connectors and co...
- Patent number 7,746,661
- Issue date Jun 29, 2010
- SanDisk Corporation
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
COL-TSOP with nonconductive material for reducing package capacitance
- Patent number 7,728,411
- Issue date Jun 1, 2010
- SanDisk Corporation
- Ming Hsun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density three dimensional semiconductor die package
- Patent number 7,663,216
- Issue date Feb 16, 2010
- SanDisk Corporation
- Cheemen Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of promoting adhesion between transfer molded IC packages a...
- Patent number 7,615,861
- Issue date Nov 10, 2009
- SanDisk Corporation
- Che-Jung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of stacking and interconnecting semiconductor packages via e...
- Patent number 7,615,409
- Issue date Nov 10, 2009
- SanDisk Corporation
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of minimizing kerf width on a semiconductor substrate panel
- Patent number 7,611,927
- Issue date Nov 3, 2009
- SanDisk Corporation
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Hidden plating traces
- Patent number 7,592,699
- Issue date Sep 22, 2009
- SanDisk Corporation
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked, interconnected semiconductor packages
- Patent number 7,550,834
- Issue date Jun 23, 2009
- SanDisk Corporation
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate warpage control and continuous electrical enhancement
- Patent number 7,538,438
- Issue date May 26, 2009
- SanDisk Corporation
- Cheemen Yu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of reducing mechanical stress on a semiconductor die during...
- Patent number 7,435,624
- Issue date Oct 14, 2008
- SanDisk Corporation
- Chin-Tien Chiu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
- Publication number 20130200507
- Publication date Aug 8, 2013
- SANDISK TECHNOLOGIES INC.
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY
- Publication number 20130084677
- Publication date Apr 4, 2013
- SANDISK TECHNOLOGIES INC.
- Ning Ye
- B82 - NANO-TECHNOLOGY
Information Patent Application
Printed Circuit Board With Coextensive Electrical Connectors And Co...
- Publication number 20120273968
- Publication date Nov 1, 2012
- Chih-Chin Liao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
- Publication number 20110210446
- Publication date Sep 1, 2011
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
- Publication number 20100289147
- Publication date Nov 18, 2010
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...
- Publication number 20100255640
- Publication date Oct 7, 2010
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE
- Publication number 20100102440
- Publication date Apr 29, 2010
- Cheemen Yu
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA E...
- Publication number 20100055835
- Publication date Mar 4, 2010
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING
- Publication number 20090321950
- Publication date Dec 31, 2009
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED...
- Publication number 20090325342
- Publication date Dec 31, 2009
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIDDEN PLATING TRACES
- Publication number 20090263969
- Publication date Oct 22, 2009
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE
- Publication number 20090256249
- Publication date Oct 15, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY PARTICLE BLASTING
- Publication number 20090085231
- Publication date Apr 2, 2009
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECE...
- Publication number 20090065902
- Publication date Mar 12, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PACKAGE STACKING USING UNBALANCED MOLDED TSOP
- Publication number 20090004783
- Publication date Jan 1, 2009
- Ming Hsun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGING IN A TSOP PACKAGE
- Publication number 20090001533
- Publication date Jan 1, 2009
- Ming Hsun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
- Publication number 20090001534
- Publication date Jan 1, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF...
- Publication number 20090001552
- Publication date Jan 1, 2009
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY
- Publication number 20090004776
- Publication date Jan 1, 2009
- Ning Ye
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CARD FABRICATED USING SIP/SMT HYBRID TECHNOLOGY
- Publication number 20090001365
- Publication date Jan 1, 2009
- Ning Ye
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
- Publication number 20090001610
- Publication date Jan 1, 2009
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING UNBALANCED MOLDED TSOP
- Publication number 20090001529
- Publication date Jan 1, 2009
- Ming Hsun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MULTI-CHIP PACKAGING IN A TSOP PACKAGE
- Publication number 20090004774
- Publication date Jan 1, 2009
- Ming Hsun Lee
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION L...
- Publication number 20090004781
- Publication date Jan 1, 2009
- Chien-Ko Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...
- Publication number 20090004782
- Publication date Jan 1, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES...
- Publication number 20090004785
- Publication date Jan 1, 2009
- Chin-Tien Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A...
- Publication number 20080303166
- Publication date Dec 11, 2008
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL
- Publication number 20080305577
- Publication date Dec 11, 2008
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE
- Publication number 20080305306
- Publication date Dec 11, 2008
- Cheemen Yu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL
- Publication number 20080305576
- Publication date Dec 11, 2008
- Cheemen Yu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Person

Patents Grantslast 30 patents

Printed circuit board with coextensive electrical connectors and co...

Molded SiP package with reinforced solder columns

Method of fabricating a memory card using SIP/SMT hybrid technology

Two-sided substrate lead connection for minimizing kerf width on a...

Rigid wave pattern design on chip carrier substrate and printed cir...

Method of fabricating stacked semiconductor package with localized...

Two-sided die in a four-sided leadframe based package

Method of fabricating a memory card using SiP/SMT hybrid technology

Stacked semiconductor package with localized cavities for wire bonding

Semiconductor die having a redistribution layer

Die package with asymmetric leadframe connection

Method of fabricating a two-sided die in a four-sided leadframe bas...

Padless substrate for surface mounted components

Semiconductor package having through holes for molding back side of...

Method of fabricating a semiconductor package having through holes...

Rounded contact fingers on substrate/PCB for crack prevention

Methods of forming a single layer substrate for high capacity memor...

Memory card fabricated using SiP/SMT hybrid technology

Method of fabricating a semiconductor die having a redistribution l...

Semiconductor die having a distribution layer

Printed circuit board with coextensive electrical connectors and co...

COL-TSOP with nonconductive material for reducing package capacitance

High density three dimensional semiconductor die package

Methods of promoting adhesion between transfer molded IC packages a...

Method of stacking and interconnecting semiconductor packages via e...

Method of minimizing kerf width on a semiconductor substrate panel

Hidden plating traces

Stacked, interconnected semiconductor packages

Substrate warpage control and continuous electrical enhancement

Method of reducing mechanical stress on a semiconductor die during...

Patents Applicationslast 30 patents

TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE

METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY

Printed Circuit Board With Coextensive Electrical Connectors And Co...

SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER

SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER

METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...

HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE

METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA E...

STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING

METHOD OF FABRICATING STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED...

HIDDEN PLATING TRACES

STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE

METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY PARTICLE BLASTING

METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECE...

METHOD OF PACKAGE STACKING USING UNBALANCED MOLDED TSOP

MULTI-CHIP PACKAGING IN A TSOP PACKAGE

TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE

SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF...

METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY

MEMORY CARD FABRICATED USING SIP/SMT HYBRID TECHNOLOGY

SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER

PACKAGE STACKING USING UNBALANCED MOLDED TSOP

METHOD OF MULTI-CHIP PACKAGING IN A TSOP PACKAGE

METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION L...

METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...

METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES...

TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A...

METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL

SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE

METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL