Patent Application
20090085231
1. Field of the Invention
Embodiments of the present invention relate to methods of smoothing the edges of a portable memory card and a memory card formed thereby.
2. Description of the Related Art
As the sizes of electronic devices continue to decrease, the associated semiconductor packages that operate within them are being designed with smaller form factors, lower power requirements and higher functionality. Currently, sub-micron features in semiconductor fabrication are placing higher demands on package technology including higher lead counts, reduced lead pitch, minimum footprint area and significant overall volume reduction.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate. The substrate may in general be a printed circuit board, a leadframe or a tape automated bonding (TAB) tape.
Once electrical connections between the die and substrate are made, the respective packages 20 on panel 22 may then typically be encapsulated in a molding compound to seal off and protect the components within the package. Once encapsulated, the respective packages 20 may be singulated from the panel 22 to form the finished packages. An example of a finished, encapsulated package is shown in prior art
Many conventional semiconductor packages, like package 20 in
Several methods are known for cutting the straight edges of a package 20 during singulation, including for example diamond saw. However, specialized cutting methods are required for cutting curvilinear shaped edges during singulation. Such specialized cutting methods include, for example, water jet cutting, laser cutting, water guided laser cutting, dry media cutting and diamond coated wire cutting. Such cutting methods are able to achieve sophisticated rectilinear and/or curvilinear shapes of the individualized integrated circuit packages. A more detailed description of methods for cutting encapsulated integrated circuits from a panel, and the shapes which may be achieved thereby, is disclosed in published U.S. Pat. No. 7,094,633, entitled “Method for Efficiently Producing Removable Peripheral Cards,” which patent is assigned to the owner of the present invention and which patent is incorporated by reference herein in its entirety.
As semiconductor packages continue to shrink, the structure within a host device for receiving and ejecting portable memory packages is becoming more delicate, and the ejection force with which smaller packages are ejected from the host device is getting smaller. Consequently, the roughness of the edges of portable memory packages is becoming a significant factor in package design, as small memory cards having rough edges may get stuck inside the host device.
Known cutting methods for cutting straight edges are effective at achieving smooth cuts. A measurement of roughness is Ra (average roughness), which is the measure of the average height of the bumps on a surface, measured for example in microns (μm). Straight edge cutting methods are typically able to achieve a roughness of Ra<1 μm. However, where a package includes curvilinear edges and is singulated by methods such as water jet or laser singulation, the edges are relatively more rough, typically about Ra=3 to 6 μm or greater. An example of a cut forming edges made by such methods is shown in prior art
The present invention, roughly described, relates to a method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. Upon completion of the abrasion process, a second cutting process may be performed which cuts along straight edges to completely singulate the respective packages from the panel.
The abrasion process may be carried out within a process tool including one or more jigs for supporting one or more panels of partially singulated semiconductor packages. The jig includes slots sized and shaped to align with the cut edges of the semiconductor packages of the panel. Once positioned on a jig within the process tool, small abrasive particles, such as for example garnets, may be supplied into the tool in an area on top of the respective semiconductor packages. The area may be filled with a fluid such as air, and may be maintained, for example, at ambient pressure.
A vacuum or low pressure area may then be created within the process tool in an area beneath the jig. This creates a pressure differential above and below the jig, and the abrasive particles are pulled down along the edges and through the slots to the lower vacuum area. The flow of the abrasive particles over time will accomplish two functions. First, the particles will smooth the jagged edges of the semiconductor packages. Second, the particles will create smooth, rounded radius edges between the top surfaces and side edges of the respective semiconductor packages. In accordance with the present invention, the abrasive particles advantageously smooth the side edges of the semiconductor packages, while leaving other surfaces, such as the top surfaces of packages, unaffected.
The particles may be evacuated from the process tool by a vacuum generator, which in turn passes the particles to a filter and recycle tank which separates the particles from particulates generated from the abrasion process. Thus, the particles may be recycled back into the process tool continuously.
The embodiments of the present invention will now be described with reference to
Referring initially to the top view of
Although not critical to the present invention, substrate 104 may be a variety of different chip carrier mediums, including a PCB, a leadframe or a TAB tape. Where substrate 104 is a PCB, the substrate may be formed of a core having top and/or bottom conductive layers formed thereon. The core may be various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like. The conductive layers may be formed of copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42FE/58NI), copper plated steel or other metals or materials known for use on substrates. The conductive layers may be etched into a conductance pattern as is known for communicating signals between the semiconductor die and an external device. A dummy pattern may also be provided in the conductive layers as is known to reduce mechanical stresses on the substrate otherwise resulting from uneven thermal expansion within the substrate. Substrate 104 may additionally include exposed metal portions forming contact pads (not shown) for receiving wire bonds and/or contact fingers (not shown) where the package 100 is an LGA package. The contact pads and/or fingers may be plated with one or more gold layers, for example in an electroplating process as is known in the art.
Where substrate 104 is a leadframe, the leadframe may be formed of a planar or substantially planar piece of metal, such as copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42Fe/58Ni), or copper plated steel. The leadframe may also be plated with silver, gold, nickel palladium, or copper. The individual leads for bonding to die 102 may be formed by photolithographic processes or mechanical stamping.
The semiconductor die 102 may be bonded to the substrate 104 in a known die bond process. After die 102 are affixed to substrate 104, wires bond 106 may be attached between bond pads on die 100 and bond pads on substrate 104. Wire bonds 106 may be affixed in a known wire bonding process and may be provided along a single side, or along two, three or four sides of die 102 and substrate 104. The package 100 may further include passive components 108, such as for example capacitors, resistors and inductors further enabling the operation of the package 100.
Once electrical connections between the die and substrate are made, the respective packages 100 may then typically be encapsulated in a molding compound 110 to seal off and protect the components within the package. Molding compound 110 may be a known epoxy such as for example available from Sumitomo Corp. and Nitto Denko Corp., both having headquarters in Japan.
After encapsulation, semiconductor packages of the prior art are typically singulated from the panel. As explained in the Background section and as shown in prior art
In the first cutting process, the curvilinear edges of the semiconductor package 100 may be cut by any of a variety of known cutting processes such as water jet cutting or laser cutting. At this point, the respective semiconductor packages are only partially cut and remain in position, fastened to the panel. The result of one embodiment of the first cutting process is shown in
After the curvilinear edges are cut, the panel may be transferred into a process tool 200, explained in greater detail below. Within process tool 200, the panel of partially singulated semiconductor packages may be supported on a jig 130 as shown in
The present invention may be advantageously used for smoothing edges formed by cutting processes which create relatively rough edges, such as for example curvilinear edges formed by water jet cutting and laser cutting. However, it is understood that the process of the present invention may be used to smooth any semiconductor package edge, straight or curvilinear, regardless of the cutting method used to cut the edge. Thus, while an embodiment of the present invention operates by first cutting the curvilinear edges, smoothing the cut edges as explained below, and then completing the singulation by then cutting the straight edges, it is understood that both curvilinear edges and straight edges may be cut in the first cutting process in alternative embodiments. In such alternative embodiments, a portion of each semiconductor package may remain uncut (preferably a portion which does not require smoothing). Thus, the packages would remain affixed to the panel when the panel is placed within the tool 200 for smoothing. In such embodiments, all cut edges may be positioned over aligned slots and smoothed. Alternatively in this embodiment, only certain cut edges may be smoothed. For example, at least some of the straight edges cut with a diamond saw may not be smoothed.
In a further embodiment, the packages 100 may be completely singulated from the panel in the first cutting process. In such embodiments, the packages may be aligned individually on jig 130 in process tool 200. Thereafter, some or all of the edges of each package may be smoothed as explained below.
The slots 132 may have a diameter of between 10 and 50 μm, and more particularly between 20 and 40 μm. It is understood that the slots 132 may be wider or narrower than these ranges in alternative embodiments. In the embodiment shown in
Referring now to
Once packages 100 are positioned on jig 130 with one or more edges 120 aligned over slots 132, a vacuum or low pressure area may be created within tool 200 in an area 156 beneath jig 130. As shown in
Particles 150 are an abrasive which over time accomplishes at least two functions. First, the particles 150 will smooth jagged edges 120 as shown in
In accordance with the present invention, the particles 150 advantageously smooth edges 120 of packages 100, while leaving other surfaces, such as surfaces 162 of packages 100 unaffected. This is because flow rate, Q, is defined by the product of the cross sectional area multiplied by the velocity over that area. The area occupied by particles 150 above surfaces 162 of packages 100 is relatively large. Thus, for a given flow rate created by the pressure differential, the velocity of particles 150 above and adjacent to surfaces 162 is relatively small. The low velocity of particles 150 above surfaces 162 imparts a relatively small kinetic energy to each of the particles, thus preventing the particles from abrading or appreciably abrading surfaces 162.
However, the cross sectional area between adjacent edges 120 of adjacent semiconductor packages 100 is relatively small. The distance between adjacent edges 120 may be no more than the width of the cut, and may for example be 50 to 100 μm. Accordingly, for the same flow rate Q, as particles 150 pass through the relatively narrow cross sectional area between adjacent semiconductor packages, the velocity of the particles 150 increases significantly as they pass along edges 120 and down through slots 132. The high speed of the moving particles creates high kinetic energy enabling the particles 150 to abrade edges 120 to create smooth edges. Moreover, the velocity of the particles 150 increases as they approach and enter the space between adjacent edges 120, thus creating the smooth radius corner. It is understood that the particles 150 may achieve high velocities and kinetic energies for abrading edges 120 by mechanisms other than having a narrow space between a pair of edges 120.
The degree of roughness of edges 120 after processing as described above may vary depending on a variety of factors. These factors include the size and shape of particles 150, the density of the particles within the tool 200, the pressure differential between the upper and lower regions of tool 200, and the length of time which the packages 100 are exposed to the pressure differential and abrasive particles 150. In embodiments, edges 120 may be processed to have a roughness, Ra, of less than 1 μm.
Referring now to
The package 100 shown in
As explained above, tool 200 may include a lower region 156 capable of having a vacuum or a lower pressure than an upper region 154. In embodiments, the only openings joining regions 154 and 156 is through slots 132 in jigs 130. In embodiments, the one or more jigs 130 within tool 200 may be seated on a table 170 within tool 200 effectively sealing off region 154 from region 156 except at slots 132. Alternatively, table 170 may be omitted, and the one or more jigs 130 themselves extend to the boundaries of the tool 200 to effectively seal off region 154 from region 156 except at slots 132.
Low pressure region 156 may be connected to a vacuum generator 174 external to tool 200. Vacuum generator 174 may be a pump or mechanism of known construction capable of drawing fluid and particles out of region 156 to create the vacuum within region 156 and the pressure differential within tool 200. The vacuum generator 174 may pump fluid and particles 150 to a filter and recycle tank 178. Filter and recycle tank 178 may use a known filtration scheme for separating the particles 150 from any particulate which may be generated during the abrading process. Thus, the particles 150 may be recycled back into tool 200 continuously.
The recycled particles 150 may be transferred from filter and recycle tank 178 to a particle supply store 180, for example by one or more pumps within or external to tank 178 and/or store 180. Store 180 may in turn be connected to process tool 200 and may supply particles 150 to ambient pressure region 156, where the particles 150 may then again be pulled down through slots 132 to vacuum region 156. In this way, particles 150 may continuously be regenerated for use within process tool 200 to smooth the edges of semiconductor packages 100. It is contemplated that from time to time the particles 150 may be replaced by new particles, either exchanging old for new particles all at once, or exchanging new for old particles gradually a little at a time.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
