Chen Feng

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit system with dummy region
- Patent number 7,741,719
- Issue date Jun 22, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Dong Sheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with dummy region
- Patent number 7,446,039
- Issue date Nov 4, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Dong Sheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing apparatus and method for forming an integrated circuit
- Patent number 7,156,726
- Issue date Jan 2, 2007
- Chartered Semiconductor Manufacturing Limited
- Feng Chen
- B24 - GRINDING POLISHING
Information Patent Grant
Extended poly buffer STI scheme
- Patent number 7,060,573
- Issue date Jun 13, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing apparatus and method for forming an integrated circuit
- Patent number 6,964,598
- Issue date Nov 15, 2005
- Chartered Semiconductor Manufacturing Limited
- Lup San Leong
- B24 - GRINDING POLISHING
Information Patent Grant
Linear polishing for improving substrate uniformity
- Patent number 6,726,545
- Issue date Apr 27, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Subramanian Balakumar
- B24 - GRINDING POLISHING
Information Patent Grant
Multiple step CMP polishing
- Patent number 6,663,472
- Issue date Dec 16, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng-Keong Lim
- B24 - GRINDING POLISHING
Information Patent Grant
Pre STI-CMP planarization scheme
- Patent number 6,664,190
- Issue date Dec 16, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Feng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation using TEOS cap and polysilicon pullback
- Patent number 6,613,648
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Limited
- Seng-Keong Victor Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for buffer STI scheme with a hard mask layer as an oxidation...
- Patent number 6,613,649
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Seng-Keong Victor Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intermetal dielectric layer for integrated circuits
- Patent number 6,528,886
- Issue date Mar 4, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation elevation uniformity via insertion of a po...
- Patent number 6,475,875
- Issue date Nov 5, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Pang Chong Hau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intermetal dielectric layer for integrated circuits
- Patent number 6,451,687
- Issue date Sep 17, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing apparatus and method for forming an integrated circuit
- Patent number 6,443,809
- Issue date Sep 3, 2002
- Chartered Semiconductor Manufacturing, Ltd.
- Lup San Leong
- B24 - GRINDING POLISHING
Information Patent Grant
Method for pre-STI-CMP planarization using poly-si thermal oxidation
- Patent number 6,436,833
- Issue date Aug 20, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Chong Hau Pang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to achieve STI planarization
- Patent number 6,403,484
- Issue date Jun 11, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing apparatus and method for forming an integrated circuit
- Patent number 6,376,378
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing, Ltd.
- Feng Chen
- B24 - GRINDING POLISHING
Information Patent Grant
Method to prevent CU dishing during damascene formation
- Patent number 6,376,376
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form shallow trench isolations without a chemical mechani...
- Patent number 6,306,723
- Issue date Oct 23, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Feng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IMD scheme by post-plasma treatment of FSG and TEOS oxide capping l...
- Patent number 6,284,644
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Arthur Khoon Siah Aug
- G01 - MEASURING TESTING
Information Patent Grant
Method to form MOS transistors with a common shallow trench isolati...
- Patent number 6,281,082
- Issue date Aug 28, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Feng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce dishing in metal chemical-mechanical polishing
- Patent number 6,274,485
- Issue date Aug 14, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Feng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form transistors and local interconnects using a silicon...
- Patent number 6,204,137
- Issue date Mar 20, 2001
- Chartered Semiconductor Manufacturing, Ltd.
- Kok Hin Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarizing local interconnects
- Patent number 6,103,569
- Issue date Aug 15, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Kok Hin Teo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR MONITORING A DEVICE
- Publication number 20210251698
- Publication date Aug 19, 2021
- Techssisted Surgical Pte Ltd
- Zenan Wang
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH DUMMY REGION
- Publication number 20090014883
- Publication date Jan 15, 2009
- Chartered Semiconductor Manufacturing LTD.
- Dong Sheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH DUMMY REGION
- Publication number 20070173016
- Publication date Jul 26, 2007
- Chartered Semiconductor Manufacturing LTD.
- Dong Sheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMP polishing heads retaining ring groove design for microscratch r...
- Publication number 20050113002
- Publication date May 26, 2005
- Feng Chen
- B24 - GRINDING POLISHING
Information Patent Application
Linear polishing for improving substrate uniformity
- Publication number 20030203710
- Publication date Oct 30, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Subramanian Balakumar
- B24 - GRINDING POLISHING
Information Patent Application
Multiple step CMP polishing
- Publication number 20030148712
- Publication date Aug 7, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng-Keong Lim
- B24 - GRINDING POLISHING
Information Patent Application
Method for buffer STI scheme with a hard mask layer as an oxidation...
- Publication number 20030104675
- Publication date Jun 5, 2003
- Seng-Keong Victor Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Intermetal dielectric layer for integrated circuits
- Publication number 20020130418
- Publication date Sep 19, 2002
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Extended poly buffer STI scheme
- Publication number 20020094648
- Publication date Jul 18, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Victor Seng Keong Lim
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Integrated circuit system with dummy region

Integrated circuit system with dummy region

Polishing apparatus and method for forming an integrated circuit

Extended poly buffer STI scheme

Polishing apparatus and method for forming an integrated circuit

Linear polishing for improving substrate uniformity

Multiple step CMP polishing

Pre STI-CMP planarization scheme

Shallow trench isolation using TEOS cap and polysilicon pullback

Method for buffer STI scheme with a hard mask layer as an oxidation...

Intermetal dielectric layer for integrated circuits

Shallow trench isolation elevation uniformity via insertion of a po...

Intermetal dielectric layer for integrated circuits

Polishing apparatus and method for forming an integrated circuit

Method for pre-STI-CMP planarization using poly-si thermal oxidation

Method to achieve STI planarization

Polishing apparatus and method for forming an integrated circuit

Method to prevent CU dishing during damascene formation

Method to form shallow trench isolations without a chemical mechani...

IMD scheme by post-plasma treatment of FSG and TEOS oxide capping l...

Method to form MOS transistors with a common shallow trench isolati...

Method to reduce dishing in metal chemical-mechanical polishing

Method to form transistors and local interconnects using a silicon...

Method for planarizing local interconnects

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR MONITORING A DEVICE

INTEGRATED CIRCUIT SYSTEM WITH DUMMY REGION

INTEGRATED CIRCUIT SYSTEM WITH DUMMY REGION

CMP polishing heads retaining ring groove design for microscratch r...

Linear polishing for improving substrate uniformity

Multiple step CMP polishing

Method for buffer STI scheme with a hard mask layer as an oxidation...

Intermetal dielectric layer for integrated circuits

Extended poly buffer STI scheme