Chester M. Nibby Jr.

Person

Beverly, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 6,311,286
- Issue date Oct 30, 2001
- NEC Corporation
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 6,125,436
- Issue date Sep 26, 2000
- NEC Corporation
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 5,956,522
- Issue date Sep 21, 1999
- Packard Bell NEC
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptively generating timing signals for access to various memory d...
- Patent number 5,809,340
- Issue date Sep 15, 1998
- Packard Bell NEC
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 5,522,069
- Issue date May 28, 1996
- Zenith Data Systems Corporation
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 5,517,648
- Issue date May 14, 1996
- Zenith Data Systems Corporation
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-on sequencing apparatus for initializing and testing a system...
- Patent number 5,491,790
- Issue date Feb 13, 1996
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system having a bus command generated by one subsys...
- Patent number 5,379,378
- Issue date Jan 3, 1995
- Bull HN Information Systems Inc.
- Arthur Peters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed burst read address generation with high speed transfer
- Patent number 5,345,573
- Issue date Sep 6, 1994
- Bull HN Information Systems Inc.
- Raymond D. Bowden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor bus access
- Patent number 5,341,501
- Issue date Aug 23, 1994
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance burst read data transfer operation
- Patent number 5,291,580
- Issue date Mar 1, 1994
- Bull HN Information Systems Inc.
- Raymond D. Bowden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Means for transferring firmware signals between a control store and...
- Patent number 4,916,601
- Issue date Apr 10, 1990
- Bull HN Information Systems Inc.
- Richard P. Kelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for loading and verifying a control store memory of a cen...
- Patent number 4,910,666
- Issue date Mar 20, 1990
- Bull HN Information Systems Inc.
- Chester M. Nibby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache resiliency in processing a variety of address faults
- Patent number 4,833,601
- Issue date May 23, 1989
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address transform method and apparatus for transferring addresses
- Patent number 4,799,222
- Issue date Jan 17, 1989
- Honeywell Bull Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pause apparatus for a memory controller with interleaved queuing ap...
- Patent number 4,558,429
- Issue date Dec 10, 1985
- Honeywell Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory identification apparatus and method
- Patent number 4,545,010
- Issue date Oct 1, 1985
- Honeywell Information Systems Inc.
- Edward R. Salas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Remap method and apparatus for a memory system which uses partially...
- Patent number 4,527,251
- Issue date Jul 2, 1985
- Honeywell Information Systems Inc.
- Chester M. Nibby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial defective chip memory support system
- Patent number 4,523,313
- Issue date Jun 11, 1985
- Honeywell Information Systems Inc.
- Chester M. Nibby
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with automatic memory configuration
- Patent number 4,507,730
- Issue date Mar 26, 1985
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identification apparatus for use in a controller to facilitate the...
- Patent number 4,468,731
- Issue date Aug 28, 1984
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with interleaved queuing apparatus
- Patent number 4,451,880
- Issue date May 29, 1984
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential word aligned addressing apparatus
- Patent number 4,432,055
- Issue date Feb 14, 1984
- Honeywell Information Systems Inc.
- Edward R. Salas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for deferring error detection of multibyte parity encoded...
- Patent number 4,388,684
- Issue date Jun 14, 1983
- Honeywell Information Systems Inc.
- Chester M. Nibby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential word aligned address apparatus
- Patent number 4,376,972
- Issue date Mar 15, 1983
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with address independent burst mode capability
- Patent number 4,370,712
- Issue date Jan 25, 1983
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft error rewrite control system
- Patent number 4,369,510
- Issue date Jan 18, 1983
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with queue control apparatus
- Patent number 4,366,538
- Issue date Dec 28, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with burst mode capability
- Patent number 4,366,539
- Issue date Dec 28, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimode memory system using a multiword common bus for double wor...
- Patent number 4,361,869
- Issue date Nov 30, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING

Chester M. Nibby Jr.

Person

Patents Grantslast 30 patents

Symmetric multiprocessing system with unified environment and distr...

Symmetric multiprocessing system with unified environment and distr...

Symmetric multiprocessing system with unified environment and distr...

Adaptively generating timing signals for access to various memory d...

Symmetric multiprocessing system with unified environment and distr...

Symmetric multiprocessing system with unified environment and distr...

Power-on sequencing apparatus for initializing and testing a system...

Data processing system having a bus command generated by one subsys...

High speed burst read address generation with high speed transfer

Processor bus access

High performance burst read data transfer operation

Means for transferring firmware signals between a control store and...

Apparatus for loading and verifying a control store memory of a cen...

Cache resiliency in processing a variety of address faults

Address transform method and apparatus for transferring addresses

Pause apparatus for a memory controller with interleaved queuing ap...

Memory identification apparatus and method

Remap method and apparatus for a memory system which uses partially...

Partial defective chip memory support system

Memory system with automatic memory configuration

Identification apparatus for use in a controller to facilitate the...

Memory controller with interleaved queuing apparatus

Sequential word aligned addressing apparatus

Apparatus for deferring error detection of multibyte parity encoded...

Sequential word aligned address apparatus

Memory controller with address independent burst mode capability

Soft error rewrite control system

Memory controller with queue control apparatus

Memory controller with burst mode capability

Multimode memory system using a multiword common bus for double wor...