Chi-Chien Ho

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Plano, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Method to improve transistor matching
- Patent number 10,339,251
- Issue date Jul 2, 2019
- Texas Instruments Incorporated
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to improve transistor matching
- Patent number 9,665,675
- Issue date May 30, 2017
- Texas Instruments Incorporated
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational lithography with feature upsizing
- Patent number 8,793,626
- Issue date Jul 29, 2014
- Texas Instruments Incorporated
- Ashesh Parikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating and operating single polysilicon flash EEPROM...
- Patent number 6,261,884
- Issue date Jul 17, 2001
- Texas Instruments Incorporated
- Chi-Chien Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Single polysilicon flash EEPROM with low positive programming and e...
- Patent number 6,054,732
- Issue date Apr 25, 2000
- Texas Instruments Incorporated
- Chi-Chien Ho
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD TO IMPROVE TRANSISTOR MATCHING
- Publication number 20170228488
- Publication date Aug 10, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO IMPROVE TRANSISTOR MATCHING
- Publication number 20150187655
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh PARIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL LITHOGRAPHY WITH FEATURE UPSIZING
- Publication number 20130254723
- Publication date Sep 26, 2013
- TEXAS INSTRUMENTS INCORPORATED
- ASHESH PARIKH
- G06 - COMPUTING CALCULATING COUNTING