Chih-Ming Tzeng

Person

Fengshan City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package structure
- Patent number 10,672,677
- Issue date Jun 2, 2020
- Industrial Technology Research Institute
- Jing-Yao Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intelligent diagnosis system for power module and method thereof
- Patent number 10,288,696
- Issue date May 14, 2019
- Industrial Technology Research Institute
- Chih-Chung Chiu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Electrically stackable semiconductor wafer and chip packages
- Patent number 9,601,474
- Issue date Mar 21, 2017
- Invensas Corporation
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer leveled chip packaging structure and method thereof
- Patent number 9,059,181
- Issue date Jun 16, 2015
- Invensas Corporation
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automatically closing hinge and electronic device using such hinge
- Patent number 8,683,649
- Issue date Apr 1, 2014
- Avision Inc.
- Chih-Chin Tzeng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Wafer-leveled chip packaging structure and method thereof
- Patent number 8,587,091
- Issue date Nov 19, 2013
- Invensas Corporation
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package device
- Patent number 8,314,482
- Issue date Nov 20, 2012
- Invensas Corporation
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing capacitance variation between capacitors
- Patent number 8,133,792
- Issue date Mar 13, 2012
- United Microelectronics Corp.
- Victor Chiang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure of capacitor set
- Patent number 8,114,752
- Issue date Feb 14, 2012
- United Microelectronics Corp.
- Victor Chiang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-leveled chip packaging structure and method thereof
- Patent number 7,528,009
- Issue date May 5, 2009
- Industrial Technology Research Institute
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-leveled chip packaging structure and method thereof
- Patent number 7,294,920
- Issue date Nov 13, 2007
- Industrial Technology Research Institute
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
POWER INTEGRATED MODULE AND MOTOR CONTROL SYSTEM
- Publication number 20240266985
- Publication date Aug 8, 2024
- Industrial Technology Research Institute
- Shian-Chiau Chiou
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
POWER MODULE
- Publication number 20240162114
- Publication date May 16, 2024
- Industrial Technology Research Institute
- Shian-Chiau Chiou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE
- Publication number 20180261519
- Publication date Sep 13, 2018
- Industrial Technology Research Institute
- Jing-Yao CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTELLIGENT DIAGNOSIS SYSTEM FOR POWER MODULE AND METHOD THEREOF
- Publication number 20180136287
- Publication date May 17, 2018
- Industrial Technology Research Institute
- Chih-Chung CHIU
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE
- Publication number 20170084521
- Publication date Mar 23, 2017
- Industrial Technology Research Institute
- Jing-Yao CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Leveled Chip Packaging Structure and Method Thereof
- Publication number 20150364457
- Publication date Dec 17, 2015
- Invensas Corporation
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Leveled Chip Packaging Structure and Method Thereof
- Publication number 20140217587
- Publication date Aug 7, 2014
- Invensas Corporation
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AUTOMATICALLY CLOSING HINGE AND ELECTRONIC DEVICE USING SUCH HINGE
- Publication number 20130119842
- Publication date May 16, 2013
- Avision Inc.
- Chih-Chin TZENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER-LEVELED CHIP PACKAGING STRUCTURE AND METHOD THEREOF
- Publication number 20120267765
- Publication date Oct 25, 2012
- Industrial Technology Research Institute
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE OF CAPACITOR SET
- Publication number 20100140741
- Publication date Jun 10, 2010
- United Microelectronics Corp.
- Victor Chiang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-VOLTAGE RADIO-FREQUENCY POWER DEVICE
- Publication number 20080251863
- Publication date Oct 16, 2008
- Sheng-Yi Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer-leveled chip packaging structure and method thereof
- Publication number 20080029870
- Publication date Feb 7, 2008
- Industrial Technology Research Institute
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE OF CAPACITOR SET AND METHOD FOR REDUCING CAPACITANCE VARI...
- Publication number 20080012092
- Publication date Jan 17, 2008
- Victor-Chiang Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer-leveled chip packaging structure and method thereof
- Publication number 20070197018
- Publication date Aug 23, 2007
- Industrial Technology Research Institute
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer-leveled chip packaging structure and method thereof
- Publication number 20060019484
- Publication date Jan 26, 2006
- Industrial Technology Research Institute
- Shou-Lung Chen
- H01 - BASIC ELECTRIC ELEMENTS

Chih-Ming Tzeng

Person

Patents Grantslast 30 patents

Semiconductor package structure

Intelligent diagnosis system for power module and method thereof

Electrically stackable semiconductor wafer and chip packages

Wafer leveled chip packaging structure and method thereof

Automatically closing hinge and electronic device using such hinge

Wafer-leveled chip packaging structure and method thereof

Semiconductor package device

Method for reducing capacitance variation between capacitors

Structure of capacitor set

Wafer-leveled chip packaging structure and method thereof

Wafer-leveled chip packaging structure and method thereof

Patents Applicationslast 30 patents

POWER INTEGRATED MODULE AND MOTOR CONTROL SYSTEM

POWER MODULE

SEMICONDUCTOR PACKAGE STRUCTURE

INTELLIGENT DIAGNOSIS SYSTEM FOR POWER MODULE AND METHOD THEREOF

SEMICONDUCTOR PACKAGE STRUCTURE

Wafer Leveled Chip Packaging Structure and Method Thereof

Wafer Leveled Chip Packaging Structure and Method Thereof

AUTOMATICALLY CLOSING HINGE AND ELECTRONIC DEVICE USING SUCH HINGE

WAFER-LEVELED CHIP PACKAGING STRUCTURE AND METHOD THEREOF

STRUCTURE OF CAPACITOR SET

HIGH-VOLTAGE RADIO-FREQUENCY POWER DEVICE

Wafer-leveled chip packaging structure and method thereof

STRUCTURE OF CAPACITOR SET AND METHOD FOR REDUCING CAPACITANCE VARI...

Wafer-leveled chip packaging structure and method thereof

Wafer-leveled chip packaging structure and method thereof