Chih-Yun CHIN

Person

Taichung City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Supportive layer in source/drains of FinFET devices
- Patent number 11,855,142
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jung-Chi Tai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interfacial layer between fin and source/drain region
- Patent number 11,735,668
- Issue date Aug 22, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interfacial layer between Fin and source/drain region
- Patent number 11,482,620
- Issue date Oct 25, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Supportive layer in source/drains of FinFET devices
- Patent number 11,476,331
- Issue date Oct 18, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jung-Chi Tai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of epitaxy and semiconductor device
- Patent number 11,264,237
- Issue date Mar 1, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interfacial layer between fin and source/drain region
- Patent number 10,944,005
- Issue date Mar 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Supportive layer in source/drains of FinFET devices
- Patent number 10,854,715
- Issue date Dec 1, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jung-Chi Tai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interfacial layer between fin and source/drain region
- Patent number 10,483,396
- Issue date Nov 19, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 10,164,097
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yen-Ru Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test apparatus
- Patent number 9,037,909
- Issue date May 19, 2015
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Chih-Jen Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Motherboard error detection system
- Patent number 8,074,114
- Issue date Dec 6, 2011
- Inventec Corporation
- Chih-Jen Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test board
- Patent number 7,940,068
- Issue date May 10, 2011
- Inventec Corporation
- Chih-Jen Chin
- G01 - MEASURING TESTING
Information Patent Grant
Holographic reticle and patterning method
- Patent number 7,722,997
- Issue date May 25, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Ming Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and apparatus for compensated illumination for advanced lith...
- Patent number 7,697,114
- Issue date Apr 13, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Ming Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
System and method for examining mask pattern fidelity
- Patent number 7,383,530
- Issue date Jun 3, 2008
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Chuan Wang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Etching bias reduction
- Patent number 7,316,872
- Issue date Jan 8, 2008
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Ming Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Holographic reticle and patterning method
- Patent number 7,312,021
- Issue date Dec 25, 2007
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Ming Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method to improve photomask critical dimension uniformity and photo...
- Patent number 7,060,400
- Issue date Jun 13, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Chuan Wang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Defect repair method employing non-defective pattern overlay and ph...
- Patent number 7,005,219
- Issue date Feb 28, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chih-Cheng Chin
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Pattern compensation for stitching
- Patent number 6,982,135
- Issue date Jan 3, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chung-Hsing Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Exchangeable module for an electric system
- Patent number 6,921,287
- Issue date Jul 26, 2005
- Phoenixtec Power Co., Ltd.
- Shark Sheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-focused ion beams for semiconductor image scanning and mask re...
- Patent number 6,653,029
- Issue date Nov 25, 2003
- Taiwan Semiconductor Manufacturing Co. Ltd
- Chuan-Yuan Lin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUPPORTIVE LAYER IN SOURCE/DRAINS OF FINFET DEVICES
- Publication number 20240096958
- Publication date Mar 21, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jung-Chi Tai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD
- Publication number 20240021618
- Publication date Jan 18, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interfacial Layer Between Fin and Source/Drain Region
- Publication number 20220376049
- Publication date Nov 24, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPPORTIVE LAYER IN SOURCE/DRAINS OF FINFET DEVICES
- Publication number 20220367630
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jung-Chi Tai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE
- Publication number 20220302281
- Publication date Sep 22, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chien-Wei LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Cluster System and Computing Node Thereof
- Publication number 20220155966
- Publication date May 19, 2022
- Inventec (Pudong) Technology Corp.
- Hsueh-Chih Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD
- Publication number 20210265350
- Publication date Aug 26, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interfacial Layer Between Fin and Source/Drain Region
- Publication number 20210193831
- Publication date Jun 24, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Supportive Layer in Source/Drains of FinFET Devices
- Publication number 20210083052
- Publication date Mar 18, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jung-Chi Tai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SERVER SWITCH SYSTEM INCLUDING FIELD-PROGRAMMABLE GATE ARRAY UNIT F...
- Publication number 20200386812
- Publication date Dec 10, 2020
- Inventec (Pudong) Technology Corp.
- Chih-Jen Chin
- G01 - MEASURING TESTING
Information Patent Application
Method of Epitaxy and Semiconductor Device
- Publication number 20200105526
- Publication date Apr 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interfacial Layer Between Fin and Source/Drain Region
- Publication number 20200006548
- Publication date Jan 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interfacial Layer Between Fin and Source/Drain Region
- Publication number 20190378920
- Publication date Dec 12, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Yun Chin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Supportive Layer in Source/Drains of FinFET Devices
- Publication number 20190319098
- Publication date Oct 17, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Roger TAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20170077300
- Publication date Mar 16, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yen-Ru LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST APPARATUS
- Publication number 20140122938
- Publication date May 1, 2014
- Inventec Corporation
- Chih-Jen Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING DEVICE
- Publication number 20130162273
- Publication date Jun 27, 2013
- Chih-Jen CHIN
- G01 - MEASURING TESTING
Information Patent Application
MONITORING SYSTEM AND METHOD OF POWER SEQUENCE SIGNAL
- Publication number 20120137159
- Publication date May 31, 2012
- Inventec Corporation
- Chih-Jen Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MONITORING INPUT/OUTPUT PORT STATUS OF PERIPH...
- Publication number 20120137027
- Publication date May 31, 2012
- Inventec Corporation
- Quan-Jie Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DETECTING CAPACITOR LOSS
- Publication number 20120133374
- Publication date May 31, 2012
- Inventec Corporation
- Chih-Jen Chin
- G01 - MEASURING TESTING
Information Patent Application
PROCESSING SYSTEM FOR MONITORING POWER-ON SELF-TEST INFORMATION
- Publication number 20120137179
- Publication date May 31, 2012
- Inventec Corporation
- Chih-Jen Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CHIP TEST SYSTEM AND TEST METHOD THEREOF
- Publication number 20120131403
- Publication date May 24, 2012
- Inventec Corporation
- CHIH-JEN CHIN
- G01 - MEASURING TESTING
Information Patent Application
TESTING MEHTOD FOR UNIT UNDER TEST
- Publication number 20120131385
- Publication date May 24, 2012
- Inventec Corporation
- CHIH-JEN CHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLUGGABLE ERROR DETECTION BOARD AND MOTHERBOARD ERROR DETECTION SYS...
- Publication number 20110055631
- Publication date Mar 3, 2011
- Inventec Corporation
- Chih-Jen CHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST BOARD
- Publication number 20100301886
- Publication date Dec 2, 2010
- Inventec Corporation
- Chih-Jen CHIN
- G01 - MEASURING TESTING
Information Patent Application
RECORDING SYSTEM AND DATA RECORDING METHOD
- Publication number 20100049903
- Publication date Feb 25, 2010
- Chih-Jen Chin
- G11 - INFORMATION STORAGE
Information Patent Application
Machine for programming on-board chipsets
- Publication number 20090189637
- Publication date Jul 30, 2009
- INVENTEC CORPORATION
- Chih-Jen Chin
- G11 - INFORMATION STORAGE
Information Patent Application
Holographic Reticle and Patterning Method
- Publication number 20080113279
- Publication date May 15, 2008
- Shih-Ming Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND APPARATUS FOR COMPENSATED ILLUMINATION FOR ADVANCED LITH...
- Publication number 20070291244
- Publication date Dec 20, 2007
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Ming CHANG
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
System and method for examining mask pattern fidelity
- Publication number 20070250805
- Publication date Oct 25, 2007
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Chuan Wang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Chih-Yun CHIN

Person

Patents Grantslast 30 patents

Supportive layer in source/drains of FinFET devices

Interfacial layer between fin and source/drain region

Interfacial layer between Fin and source/drain region

Supportive layer in source/drains of FinFET devices

Method of epitaxy and semiconductor device

Interfacial layer between fin and source/drain region

Supportive layer in source/drains of FinFET devices

Interfacial layer between fin and source/drain region

Semiconductor device and manufacturing method thereof

Test apparatus

Motherboard error detection system

Test board

Holographic reticle and patterning method

Method and apparatus for compensated illumination for advanced lith...

System and method for examining mask pattern fidelity

Etching bias reduction

Holographic reticle and patterning method

Method to improve photomask critical dimension uniformity and photo...

Defect repair method employing non-defective pattern overlay and ph...

Pattern compensation for stitching

Exchangeable module for an electric system

Dual-focused ion beams for semiconductor image scanning and mask re...

Patents Applicationslast 30 patents

SUPPORTIVE LAYER IN SOURCE/DRAINS OF FINFET DEVICES

SEMICONDUCTOR DEVICE AND METHOD

Interfacial Layer Between Fin and Source/Drain Region

SUPPORTIVE LAYER IN SOURCE/DRAINS OF FINFET DEVICES

SOURCE/DRAIN STRUCTURE FOR SEMICONDUCTOR DEVICE

Hybrid Cluster System and Computing Node Thereof

SEMICONDUCTOR DEVICE AND METHOD

Interfacial Layer Between Fin and Source/Drain Region

Supportive Layer in Source/Drains of FinFET Devices

SERVER SWITCH SYSTEM INCLUDING FIELD-PROGRAMMABLE GATE ARRAY UNIT F...

Method of Epitaxy and Semiconductor Device

Interfacial Layer Between Fin and Source/Drain Region

Interfacial Layer Between Fin and Source/Drain Region

Supportive Layer in Source/Drains of FinFET Devices

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TEST APPARATUS

TESTING DEVICE

MONITORING SYSTEM AND METHOD OF POWER SEQUENCE SIGNAL

SYSTEM AND METHOD FOR MONITORING INPUT/OUTPUT PORT STATUS OF PERIPH...

METHOD FOR DETECTING CAPACITOR LOSS

PROCESSING SYSTEM FOR MONITORING POWER-ON SELF-TEST INFORMATION

MULTI-CHIP TEST SYSTEM AND TEST METHOD THEREOF

TESTING MEHTOD FOR UNIT UNDER TEST

PLUGGABLE ERROR DETECTION BOARD AND MOTHERBOARD ERROR DETECTION SYS...

TEST BOARD

RECORDING SYSTEM AND DATA RECORDING METHOD

Machine for programming on-board chipsets

Holographic Reticle and Patterning Method

METHOD AND APPARATUS FOR COMPENSATED ILLUMINATION FOR ADVANCED LITH...

System and method for examining mask pattern fidelity