Ching-Lung Tong

Person

Highland Mills, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase aligning and calibrating clocks from one phase lock loop (PLL...
- Patent number 12,111,684
- Issue date Oct 8, 2024
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase aligning and calibrating clocks from one phase lock loop (PLL...
- Patent number 11,775,004
- Issue date Oct 3, 2023
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency data transfer between clock domains operated in various...
- Patent number 8,898,503
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit arrangement for test inputs
- Patent number 8,479,070
- Issue date Jul 2, 2013
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for generating synchronization signals for syn...
- Patent number 8,295,419
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Charlie C. Hwang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating synchronization signals for syn...
- Patent number 7,826,579
- Issue date Nov 2, 2010
- International Business Machines Corporation
- Charlie C. Hwang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to prevent firmware defects from disturbing logic clocks to...
- Patent number 7,568,138
- Issue date Jul 28, 2009
- International Business Machines Corporation
- Adolf Martens
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to self-synchronize clocks on multiple chips in a system
- Patent number 7,382,844
- Issue date Jun 3, 2008
- International Business Machines Corporation
- Charlie C. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measuring microprocessor susceptibility to internal noise generation
- Patent number 7,313,747
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Sungjun Chun
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for controlling clocks in a processor with mir...
- Patent number 7,146,520
- Issue date Dec 5, 2006
- International Business Machines Corporation
- Michael Billeci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for characterizing coupling capacitance between i...
- Patent number 6,333,680
- Issue date Dec 25, 2001
- International Business Machines Corporation
- Howard H. Smith
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...
- Publication number 20230393610
- Publication date Dec 7, 2023
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...
- Publication number 20230085155
- Publication date Mar 16, 2023
- International Business Machines Corporation
- Douglas J. Malone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY DATA TRANSFER BETWEEN CLOCK DOMAINS OPERATED IN VARIOUS...
- Publication number 20140136737
- Publication date May 15, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Arrangement For Test Inputs
- Publication number 20110320898
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Application
Method and Apparatus for Generating Synchronization Signals for Syn...
- Publication number 20110033017
- Publication date Feb 10, 2011
- International Business Machines Corporation
- Charlie C. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO PREVENT FIRMWARE DEFECTS FROM DISTURBING LOGIC CLOCKS TO...
- Publication number 20080028266
- Publication date Jan 31, 2008
- Adolf Martens
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Measuring microprocessor susceptibility to internal noise generation
- Publication number 20070236299
- Publication date Oct 11, 2007
- Sungjun Chun
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for generating synchronization signals for syn...
- Publication number 20060182212
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Charlie C. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods to self-synchronize clocks on multiple chips in a system
- Publication number 20060182214
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Charlie C. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling clocks in a processor with mir...
- Publication number 20040230857
- Publication date Nov 18, 2004
- International Business Machines Corporation
- Michael Billeci
- G06 - COMPUTING CALCULATING COUNTING

Ching-Lung Tong

Person

Patents Grantslast 30 patents

Phase aligning and calibrating clocks from one phase lock loop (PLL...

Phase aligning and calibrating clocks from one phase lock loop (PLL...

Low latency data transfer between clock domains operated in various...

Integrated circuit arrangement for test inputs

Method and apparatus for generating synchronization signals for syn...

Method and apparatus for generating synchronization signals for syn...

Method to prevent firmware defects from disturbing logic clocks to...

Methods to self-synchronize clocks on multiple chips in a system

Measuring microprocessor susceptibility to internal noise generation

Method and apparatus for controlling clocks in a processor with mir...

Method and system for characterizing coupling capacitance between i...

Patents Applicationslast 30 patents

PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...

PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL...

LOW LATENCY DATA TRANSFER BETWEEN CLOCK DOMAINS OPERATED IN VARIOUS...

Integrated Circuit Arrangement For Test Inputs

Method and Apparatus for Generating Synchronization Signals for Syn...

METHOD TO PREVENT FIRMWARE DEFECTS FROM DISTURBING LOGIC CLOCKS TO...

Measuring microprocessor susceptibility to internal noise generation

Method and apparatus for generating synchronization signals for syn...

Methods to self-synchronize clocks on multiple chips in a system

Method and apparatus for controlling clocks in a processor with mir...