Ching-Nen Peng

Person

Hsin-Chu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Test circuit and method
- Patent number 11,852,672
- Issue date Dec 26, 2023
- TAIWAN SEMICONDUCTORMANUFACTURING COMPANY LIMITED
- Mill-Jer Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromagnetic shielding during wafer stage testing
- Patent number 11,726,112
- Issue date Aug 15, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ching-Nen Peng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 11,579,190
- Issue date Feb 14, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit and method
- Patent number 11,467,203
- Issue date Oct 11, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite integrated circuits and methods for wireless interactions...
- Patent number 11,387,683
- Issue date Jul 12, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Min-Jer Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 11,340,291
- Issue date May 24, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Devices for high-density probing techniques and method of implement...
- Patent number 11,249,112
- Issue date Feb 15, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Alignment testing for tiered semiconductor structure
- Patent number 11,231,453
- Issue date Jan 25, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Three dimensional integrated circuit electrostatic discharge protec...
- Patent number 11,229,109
- Issue date Jan 18, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Composite integrated circuits and methods for wireless interactions...
- Patent number 10,790,707
- Issue date Sep 29, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Min-Jer Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuit and method
- Patent number 10,725,090
- Issue date Jul 28, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Devices for high-density probing techniques and method of implement...
- Patent number 10,718,790
- Issue date Jul 21, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 10,698,026
- Issue date Jun 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Three dimensional integrated circuit electrostatic discharge protec...
- Patent number 10,652,987
- Issue date May 12, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Devices for high-density probing techniques and method of implement...
- Patent number 10,274,518
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Composite integrated circuits and methods for wireless interactions...
- Patent number 10,164,480
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Jer Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment testing for tiered semiconductor structure
- Patent number 10,073,135
- Issue date Sep 11, 2018
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 10,067,181
- Issue date Sep 4, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 10,002,829
- Issue date Jun 19, 2018
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for three dimensional integrated circuit testing
- Patent number 9,952,279
- Issue date Apr 24, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Integrated fan-out pillar probe system
- Patent number 9,915,699
- Issue date Mar 13, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Three dimensional integrated circuit electrostatic discharge protec...
- Patent number 9,900,970
- Issue date Feb 20, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Test circuit and method
- Patent number 9,891,266
- Issue date Feb 13, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Systems for probing semiconductor wafers
- Patent number 9,880,201
- Issue date Jan 30, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Circuit probing structures and methods for probing the same
- Patent number 9,754,847
- Issue date Sep 5, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D IC testing apparatus
- Patent number 9,671,457
- Issue date Jun 6, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 9,664,707
- Issue date May 30, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Alignment testing for tiered semiconductor structure
- Patent number 9,658,281
- Issue date May 23, 2017
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Composite integrated circuits and methods for wireless interactions...
- Patent number 9,653,927
- Issue date May 16, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd
- Min-Jer Wang
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Test circuit and method
- Patent number 9,640,447
- Issue date May 2, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TEST CIRCUIT AND METHOD
- Publication number 20220357389
- Publication date Nov 10, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20220283221
- Publication date Sep 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
ELECTROMAGNETIC SHIELDING DURING WAFER STAGE TESTING
- Publication number 20210080487
- Publication date Mar 18, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ching-Nen Peng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS...
- Publication number 20210013748
- Publication date Jan 14, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Jer Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST CIRCUIT AND METHOD
- Publication number 20200355737
- Publication date Nov 12, 2020
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENT...
- Publication number 20200348341
- Publication date Nov 5, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20200326370
- Publication date Oct 15, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
- Publication number 20200264227
- Publication date Aug 20, 2020
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTEC...
- Publication number 20200245439
- Publication date Jul 30, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENT...
- Publication number 20190302146
- Publication date Oct 3, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
Composite Integrated Circuits and Methods for Wireless Interactions...
- Publication number 20190140488
- Publication date May 9, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20180372796
- Publication date Dec 27, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT AND METHOD
- Publication number 20180164365
- Publication date Jun 14, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTEC...
- Publication number 20180153026
- Publication date May 31, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
- Publication number 20170254849
- Publication date Sep 7, 2017
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20170248652
- Publication date Aug 31, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS...
- Publication number 20170242071
- Publication date Aug 24, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20170154843
- Publication date Jun 1, 2017
- Taiwan Semiconductor Manufacturing company Ltd.
- HAO CHEN
- G01 - MEASURING TESTING
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20160370407
- Publication date Dec 22, 2016
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENT...
- Publication number 20160313372
- Publication date Oct 27, 2016
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20160223584
- Publication date Aug 4, 2016
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTEC...
- Publication number 20160113099
- Publication date Apr 21, 2016
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer WANG
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED FAN-OUT PILLAR PROBE SYSTEM
- Publication number 20160077147
- Publication date Mar 17, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
Circuit Probing Structures and Methods for Probing the Same
- Publication number 20150380328
- Publication date Dec 31, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS...
- Publication number 20150323589
- Publication date Nov 12, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Min-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
PORTABLE ANALYTICAL DEVICE AND SYSTEM
- Publication number 20150265193
- Publication date Sep 24, 2015
- Industrial Technology Research Institute
- Hui-Hsin Lu
- G01 - MEASURING TESTING
Information Patent Application
Test Circuit And Method
- Publication number 20150241507
- Publication date Aug 27, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
Test Circuit And Method
- Publication number 20150241508
- Publication date Aug 27, 2015
- Taiwan Semiconductor Manufacturing CO.,LTD.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED FAN-OUT WAFER ARCHITECTURE AND TEST METHOD
- Publication number 20150198662
- Publication date Jul 16, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED FAN-OUT PACKAGE-ON-PACKAGE TESTING
- Publication number 20150185282
- Publication date Jul 2, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Mill-Jer WANG
- G01 - MEASURING TESTING

Ching-Nen Peng

Person

Patents Grantslast 30 patents

Test circuit and method

Electromagnetic shielding during wafer stage testing

Testing holders for chip unit and die package

Test circuit and method

Composite integrated circuits and methods for wireless interactions...

Testing holders for chip unit and die package

Devices for high-density probing techniques and method of implement...

Alignment testing for tiered semiconductor structure

Three dimensional integrated circuit electrostatic discharge protec...

Composite integrated circuits and methods for wireless interactions...

Test circuit and method

Devices for high-density probing techniques and method of implement...

Testing holders for chip unit and die package

Three dimensional integrated circuit electrostatic discharge protec...

Devices for high-density probing techniques and method of implement...

Composite integrated circuits and methods for wireless interactions...

Alignment testing for tiered semiconductor structure

Testing holders for chip unit and die package

Semiconductor device and manufacturing method thereof

Apparatus for three dimensional integrated circuit testing

Integrated fan-out pillar probe system

Three dimensional integrated circuit electrostatic discharge protec...

Test circuit and method

Systems for probing semiconductor wafers

Circuit probing structures and methods for probing the same

3D IC testing apparatus

Testing holders for chip unit and die package

Alignment testing for tiered semiconductor structure

Composite integrated circuits and methods for wireless interactions...

Test circuit and method

Patents Applicationslast 30 patents

TEST CIRCUIT AND METHOD

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

ELECTROMAGNETIC SHIELDING DURING WAFER STAGE TESTING

COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS...

TEST CIRCUIT AND METHOD

DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENT...

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE

THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTEC...

DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENT...

Composite Integrated Circuits and Methods for Wireless Interactions...

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

TEST CIRCUIT AND METHOD

THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTEC...

ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENT...

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTEC...

INTEGRATED FAN-OUT PILLAR PROBE SYSTEM

Circuit Probing Structures and Methods for Probing the Same

COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS...

PORTABLE ANALYTICAL DEVICE AND SYSTEM

Test Circuit And Method

Test Circuit And Method

INTEGRATED FAN-OUT WAFER ARCHITECTURE AND TEST METHOD

INTEGRATED FAN-OUT PACKAGE-ON-PACKAGE TESTING