Chong Lee

Person

San Ramon, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-protocol configurable transceiver including configurable desk...
- Patent number 10,216,219
- Issue date Feb 26, 2019
- Altera Corporation
- Divya Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable multi-lane scrambler for flexible protocol support
- Patent number 10,009,198
- Issue date Jun 26, 2018
- Altera Corporation
- Curt Wortman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-protocol configurable transceiver including configurable desk...
- Patent number 9,531,646
- Issue date Dec 27, 2016
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 9,438,272
- Issue date Sep 6, 2016
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable multi-lane scrambler for flexible protocol support
- Patent number 9,367,509
- Issue date Jun 14, 2016
- Altera Corporation
- Curt Wortman
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods of dynamic transmit equalization
- Patent number 9,270,500
- Issue date Feb 23, 2016
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable multi-standard device interface
- Patent number 9,170,952
- Issue date Oct 27, 2015
- Altera Corporation
- Divya Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 9,077,330
- Issue date Jul 7, 2015
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for operating a communication circuit during a lo...
- Patent number 9,049,120
- Issue date Jun 2, 2015
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for transitioning a communication circuit to a lo...
- Patent number 8,989,284
- Issue date Mar 24, 2015
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for operating a communication circuit configurabl...
- Patent number 8,984,380
- Issue date Mar 17, 2015
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable multi-lane scrambler for flexible protocol support
- Patent number 8,949,493
- Issue date Feb 3, 2015
- Altera Corporation
- Curt Wortman
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 8,804,890
- Issue date Aug 12, 2014
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for efficiently transitioning a communication cir...
- Patent number 8,788,862
- Issue date Jul 22, 2014
- Altera Corporation
- Divya Vijayaraghavan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Heterogeneous transceiver architecture for wide range programmabili...
- Patent number 8,787,352
- Issue date Jul 22, 2014
- Altera Corporation
- Sergey Shumarayev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-protocol configurable transceiver with independent channel-ba...
- Patent number 8,732,375
- Issue date May 20, 2014
- Altera Corporation
- Divya Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods of dynamic transmit equalization
- Patent number 8,630,198
- Issue date Jan 14, 2014
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 8,570,197
- Issue date Oct 29, 2013
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-protocol multiple-data-rate auto-speed negotiation architectu...
- Patent number 8,477,831
- Issue date Jul 2, 2013
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 8,462,908
- Issue date Jun 11, 2013
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible interface for stacked protocol in a programmable integrate...
- Patent number 8,458,383
- Issue date Jun 4, 2013
- Altera Corporation
- Curt Wortman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Oversampling with programmable pointer adjustment
- Patent number 8,363,770
- Issue date Jan 29, 2013
- Altera Corporation
- Ning Xue
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
CDR control architecture for robust low-latency exit from the power...
- Patent number 8,291,255
- Issue date Oct 16, 2012
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-protocol channel-aggregated configurable transceiver in an in...
- Patent number 8,165,191
- Issue date Apr 24, 2012
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for standby voltage offset cancellation
- Patent number 8,098,087
- Issue date Jan 17, 2012
- Altera Corporation
- John Dung-Ngoc Lam
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data interface methods and circuitry with reduced latency
- Patent number 7,984,209
- Issue date Jul 19, 2011
- Altera Corporation
- Vinson Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous transceiver architecture for wide range programmabili...
- Patent number 7,940,814
- Issue date May 10, 2011
- Altera Corporation
- Sergey Shumarayev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
CDR control architecture for robust low-latency exit from the power...
- Patent number 7,925,913
- Issue date Apr 12, 2011
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Field programmable gate array architectures and methods for support...
- Patent number 7,869,343
- Issue date Jan 11, 2011
- Altera Corporation
- Ning Xue
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 7,869,553
- Issue date Jan 11, 2011
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Clock Data Recovery Circuitry Associated With Programmable Logic De...
- Publication number 20170155529
- Publication date Jun 1, 2017
- Altera Corporation
- Edward Aung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONFIGURABLE MULTI-LANE SCRAMBLER FOR FLEXIBLE PROTOCOL SUPPORT
- Publication number 20160277221
- Publication date Sep 22, 2016
- Altera Corporation
- Curt Wortman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE MULTI-LANE SCRAMBLER FOR FLEXIBLE PROTOCOL SUPPORT
- Publication number 20150127856
- Publication date May 7, 2015
- Altera Corporation
- Curt Wortman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...
- Publication number 20140009188
- Publication date Jan 9, 2014
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS
- Publication number 20130265179
- Publication date Oct 10, 2013
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-PROTOCOL MULTIPLE-DATA-RATE AUTO-SPEED NEGOTIATION ARCHITECTU...
- Publication number 20120307878
- Publication date Dec 6, 2012
- Altera Corporation
- Divya Vijayaraghavan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILI...
- Publication number 20110211621
- Publication date Sep 1, 2011
- Altera Corporation
- Sergey Shumarayev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS
- Publication number 20110090101
- Publication date Apr 21, 2011
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...
- Publication number 20110068845
- Publication date Mar 24, 2011
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EMBEDDED DIGITAL IP STRIP CHIP
- Publication number 20100277201
- Publication date Nov 4, 2010
- Curt Wortman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-protocol channel-aggregated configurable transceiver in an in...
- Publication number 20100215086
- Publication date Aug 26, 2010
- Altera Corporation
- Divya Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILI...
- Publication number 20100058099
- Publication date Mar 4, 2010
- Altera Corporation
- Sergey Shumarayev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock data recovery circuitry associated with programmable logic de...
- Publication number 20080031385
- Publication date Feb 7, 2008
- Altera Corporation
- Edward Aung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Heterogeneous transceiver architecture for wide range programmabili...
- Publication number 20070237186
- Publication date Oct 11, 2007
- Altera Corporation
- Sergey Shumarayev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT
- Publication number 20070188189
- Publication date Aug 16, 2007
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Next generation 8B10B architecture
- Publication number 20070139232
- Publication date Jun 21, 2007
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device architecture for accommodating specialize...
- Publication number 20070063733
- Publication date Mar 22, 2007
- Altera Corporation
- Sergey Y. Shumarayev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-channel communication circuitry for programmable logic device...
- Publication number 20070058618
- Publication date Mar 15, 2007
- Altera Corporation
- Thungoc Tran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Deserializer circuitry for high-speed serial data receivers on prog...
- Publication number 20070043991
- Publication date Feb 22, 2007
- Altera Corporation
- Toan Thanh Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Serializer circuitry for high-speed serial data transmitters on pro...
- Publication number 20070030184
- Publication date Feb 8, 2007
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multiple data rates in programmable logic device serial interface
- Publication number 20070011370
- Publication date Jan 11, 2007
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multiple data rates in programmable logic device serial interface
- Publication number 20060233172
- Publication date Oct 19, 2006
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with high speed serial interface circuitry
- Publication number 20060095605
- Publication date May 4, 2006
- Chong H. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Next generation 8B10B architecture
- Publication number 20060095613
- Publication date May 4, 2006
- Altera Corporation
- Ramanand Venkata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic devices with multi-standard byte synchronization...
- Publication number 20060012394
- Publication date Jan 19, 2006
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable logic device with high speed serial interface circuitry
- Publication number 20050212556
- Publication date Sep 29, 2005
- Altera Corporation
- Chong H. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Run-length violation detection circuitry and methods for using the...
- Publication number 20050162289
- Publication date Jul 28, 2005
- Altera Corporation
- Vinson Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage controlled oscillator programmable delay cells
- Publication number 20050024158
- Publication date Feb 3, 2005
- Altera Corporation
- Stjepan William Andrasic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices with multi-standard byte synchronization...
- Publication number 20050007996
- Publication date Jan 13, 2005
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital phase locked loop circuitry and methods
- Publication number 20040140837
- Publication date Jul 22, 2004
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Multi-protocol configurable transceiver including configurable desk...

Configurable multi-lane scrambler for flexible protocol support

Multi-protocol configurable transceiver including configurable desk...

Digital phase locked loop circuitry and methods

Configurable multi-lane scrambler for flexible protocol support

Apparatus and methods of dynamic transmit equalization

Configurable multi-standard device interface

Serializer circuitry for high-speed serial data transmitters on pro...

Method and system for operating a communication circuit during a lo...

Method and system for transitioning a communication circuit to a lo...

Method and system for operating a communication circuit configurabl...

Configurable multi-lane scrambler for flexible protocol support

Digital phase locked loop circuitry and methods

Method and system for efficiently transitioning a communication cir...

Heterogeneous transceiver architecture for wide range programmabili...

Multi-protocol configurable transceiver with independent channel-ba...

Apparatus and methods of dynamic transmit equalization

Serializer circuitry for high-speed serial data transmitters on pro...

Multi-protocol multiple-data-rate auto-speed negotiation architectu...

Digital phase locked loop circuitry and methods

Flexible interface for stacked protocol in a programmable integrate...

Oversampling with programmable pointer adjustment

CDR control architecture for robust low-latency exit from the power...

Multi-protocol channel-aggregated configurable transceiver in an in...

Method and apparatus for standby voltage offset cancellation

Data interface methods and circuitry with reduced latency

Heterogeneous transceiver architecture for wide range programmabili...

CDR control architecture for robust low-latency exit from the power...

Field programmable gate array architectures and methods for support...

Digital phase locked loop circuitry and methods

Patents Applicationslast 30 patents

Clock Data Recovery Circuitry Associated With Programmable Logic De...

CONFIGURABLE MULTI-LANE SCRAMBLER FOR FLEXIBLE PROTOCOL SUPPORT

CONFIGURABLE MULTI-LANE SCRAMBLER FOR FLEXIBLE PROTOCOL SUPPORT

SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...

DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS

MULTI-PROTOCOL MULTIPLE-DATA-RATE AUTO-SPEED NEGOTIATION ARCHITECTU...

HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILI...

DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS

SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...

EMBEDDED DIGITAL IP STRIP CHIP

Multi-protocol channel-aggregated configurable transceiver in an in...

HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILI...

Clock data recovery circuitry associated with programmable logic de...

Heterogeneous transceiver architecture for wide range programmabili...

PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT

Next generation 8B10B architecture

Programmable logic device architecture for accommodating specialize...

Multi-channel communication circuitry for programmable logic device...

Deserializer circuitry for high-speed serial data receivers on prog...

Serializer circuitry for high-speed serial data transmitters on pro...

Multiple data rates in programmable logic device serial interface

Multiple data rates in programmable logic device serial interface

Programmable logic device with high speed serial interface circuitry

Next generation 8B10B architecture

Programmable logic devices with multi-standard byte synchronization...

Programmable logic device with high speed serial interface circuitry

Run-length violation detection circuitry and methods for using the...

Voltage controlled oscillator programmable delay cells

Programmable logic devices with multi-standard byte synchronization...

Digital phase locked loop circuitry and methods