Choong Kooi Chee

Person

Penang, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Face-to-face through-silicon via multi-chip semiconductor apparatus...
- Patent number 12,237,245
- Issue date Feb 25, 2025
- Altera Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Face-to-face through-silicon via multi-chip semiconductor apparatus...
- Patent number 12,125,768
- Issue date Oct 22, 2024
- Altera Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 12,112,997
- Issue date Oct 8, 2024
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 12,080,628
- Issue date Sep 3, 2024
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip assemblies
- Patent number 11,805,602
- Issue date Oct 31, 2023
- Intel Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 11,652,026
- Issue date May 16, 2023
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded dual-sided interconnect bridges for integrated-circuit pac...
- Patent number 11,562,959
- Issue date Jan 24, 2023
- Intel Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked semiconductor package with flyover bridge
- Patent number 11,527,481
- Issue date Dec 13, 2022
- Intel Corporation
- Choong Kooi Chee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked through-silicon vias for multi-device packages
- Patent number 11,398,415
- Issue date Jul 26, 2022
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 11,393,741
- Issue date Jul 19, 2022
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Face-to-face through-silicon via multi-chip semiconductor apparatus...
- Patent number 11,107,751
- Issue date Aug 31, 2021
- Intel Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 10,903,142
- Issue date Jan 26, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device attachment on a reverse microelectronic package
- Patent number 10,136,516
- Issue date Nov 20, 2018
- Intel Corporation
- Howe Yin Loo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnection of an embedded die
- Patent number 9,978,735
- Issue date May 22, 2018
- Altera Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device attachment on a reverse microelectronic package
- Patent number 9,699,904
- Issue date Jul 4, 2017
- Intel Corporation
- Howe Yin Loo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package on wide I/O silicon
- Patent number 9,159,714
- Issue date Oct 13, 2015
- Intel Corporation
- Jenny Shio Yin Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside mold process for ultra thin substrate and package on packa...
- Patent number 8,835,220
- Issue date Sep 16, 2014
- Intel Corporation
- Huay Huay Sim
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Backside mold process for ultra thin substrate and package on packa...
- Patent number 8,384,223
- Issue date Feb 26, 2013
- Intel Corporation
- Huay Huay Sim
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Underfilling process in a molded matrix array package using flow fr...
- Patent number 7,339,276
- Issue date Mar 4, 2008
- Intel Corporation
- Rahul N. Manepalli
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Capillary underfill and mold encapsulation method and apparatus
- Patent number 7,262,077
- Issue date Aug 28, 2007
- Intel Corporation
- Yin Men Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Underfilling process in a molded matrix array package using flow fr...
- Patent number 7,151,014
- Issue date Dec 19, 2006
- Intel Corporation
- Rahul N. Manepalli
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip packaging compositions, packages and systems made therewith, a...
- Patent number 7,088,010
- Issue date Aug 8, 2006
- Intel Corporation
- Sheau Hooi Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress-compensation layers in contact arrays, and processes of maki...
- Patent number 7,005,321
- Issue date Feb 28, 2006
- Intel Corporation
- Choong Kooi Chee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Protected bond fingers
- Patent number 6,774,471
- Issue date Aug 10, 2004
- Intel Corporation
- Choong Kooi Chee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...
- Publication number 20250022774
- Publication date Jan 16, 2025
- Altera Corporation
- Loke Yip FOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20240429131
- Publication date Dec 26, 2024
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20230361003
- Publication date Nov 9, 2023
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20230253295
- Publication date Aug 10, 2023
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...
- Publication number 20230137035
- Publication date May 4, 2023
- Intel Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20220157694
- Publication date May 19, 2022
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ASSEMBLIES
- Publication number 20220078914
- Publication date Mar 10, 2022
- Intel Corporation
- Loke Yip FOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR PACKAGE WITH FLYOVER BRIDGE
- Publication number 20220077070
- Publication date Mar 10, 2022
- Intel Corporation
- Choong Kooi CHEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...
- Publication number 20210391238
- Publication date Dec 16, 2021
- Intel Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20210320051
- Publication date Oct 14, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED DUAL-SIDED INTERCONNECT BRIDGES FOR INTEGRATED-CIRCUIT PAC...
- Publication number 20210098375
- Publication date Apr 1, 2021
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED THROUGH-SILICON VIAS FOR MULTI-DEVICE PACKAGES
- Publication number 20200091040
- Publication date Mar 19, 2020
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20200043831
- Publication date Feb 6, 2020
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...
- Publication number 20190304876
- Publication date Oct 3, 2019
- Intel Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTION OF AN EMBEDDED DIE
- Publication number 20180090474
- Publication date Mar 29, 2018
- Altera Corporation
- Loke Yip Foo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE ATTACHMENT ON A REVERSE MICROELECTRONIC PACKAGE
- Publication number 20170265306
- Publication date Sep 14, 2017
- Intel Corporation
- Howe Yin Loo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ON WIDE I/O SILICON
- Publication number 20150091180
- Publication date Apr 2, 2015
- Jenny Shio Yin ONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKA...
- Publication number 20150072474
- Publication date Mar 12, 2015
- Intel Corporation
- Huay Huay Sim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE ATTACHMENT ON A REVERSE MICROELECTRONIC PACKAGE
- Publication number 20140293563
- Publication date Oct 2, 2014
- Howe Yin Loo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKA...
- Publication number 20130230946
- Publication date Sep 5, 2013
- Huay Huay Sim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKA...
- Publication number 20090321949
- Publication date Dec 31, 2009
- Huay Huay Sim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPILLARY UNDERFILL AND MOLD ENCAPSULATION METHOD AND APPARATUS
- Publication number 20080017976
- Publication date Jan 24, 2008
- Intel Corporation
- Yin Men Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capillary underfill and mold encapsulation method and apparatus
- Publication number 20060214311
- Publication date Sep 28, 2006
- Yin Men Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stress-compensation layers in contact arrays, and processes of maki...
- Publication number 20050221532
- Publication date Oct 6, 2005
- Choong Kooi Chee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip packaging compositions, packages and systems made therewith, a...
- Publication number 20050133938
- Publication date Jun 23, 2005
- Intel Corporation
- Sheau Hooi Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Underfilling process in a molded matrix array package using flow fr...
- Publication number 20040157369
- Publication date Aug 12, 2004
- Rahul N. Manepalli
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Underfilling process in a molded matrix array package using flow fr...
- Publication number 20040084209
- Publication date May 6, 2004
- Rahul N. Manepalli
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Protected bond fingers
- Publication number 20030203542
- Publication date Oct 30, 2003
- Choong Kooi Chee
- H01 - BASIC ELECTRIC ELEMENTS

Choong Kooi Chee

Person

Patents Grantslast 30 patents

Face-to-face through-silicon via multi-chip semiconductor apparatus...

Face-to-face through-silicon via multi-chip semiconductor apparatus...

Micro through-silicon via for transistor density scaling

Micro through-silicon via for transistor density scaling

Chip assemblies

Micro through-silicon via for transistor density scaling

Embedded dual-sided interconnect bridges for integrated-circuit pac...

Stacked semiconductor package with flyover bridge

Stacked through-silicon vias for multi-device packages

Micro through-silicon via for transistor density scaling

Face-to-face through-silicon via multi-chip semiconductor apparatus...

Micro through-silicon via for transistor density scaling

Microelectronic device attachment on a reverse microelectronic package

Interconnection of an embedded die

Microelectronic device attachment on a reverse microelectronic package

Package on wide I/O silicon

Backside mold process for ultra thin substrate and package on packa...

Backside mold process for ultra thin substrate and package on packa...

Underfilling process in a molded matrix array package using flow fr...

Capillary underfill and mold encapsulation method and apparatus

Underfilling process in a molded matrix array package using flow fr...

Chip packaging compositions, packages and systems made therewith, a...

Stress-compensation layers in contact arrays, and processes of maki...

Protected bond fingers

Patents Applicationslast 30 patents

FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

CHIP ASSEMBLIES

STACKED SEMICONDUCTOR PACKAGE WITH FLYOVER BRIDGE

FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

EMBEDDED DUAL-SIDED INTERCONNECT BRIDGES FOR INTEGRATED-CIRCUIT PAC...

STACKED THROUGH-SILICON VIAS FOR MULTI-DEVICE PACKAGES

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS...

INTERCONNECTION OF AN EMBEDDED DIE

MICROELECTRONIC DEVICE ATTACHMENT ON A REVERSE MICROELECTRONIC PACKAGE

PACKAGE ON WIDE I/O SILICON

BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKA...

MICROELECTRONIC DEVICE ATTACHMENT ON A REVERSE MICROELECTRONIC PACKAGE

BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKA...

BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKA...

CAPILLARY UNDERFILL AND MOLD ENCAPSULATION METHOD AND APPARATUS

Capillary underfill and mold encapsulation method and apparatus

Stress-compensation layers in contact arrays, and processes of maki...

Chip packaging compositions, packages and systems made therewith, a...

Underfilling process in a molded matrix array package using flow fr...

Underfilling process in a molded matrix array package using flow fr...

Protected bond fingers