Christopher Lane

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dielectric liners on through glass vias
- Patent number 12,087,623
- Issue date Sep 10, 2024
- YIELD ENGINEERING SYSTEMS, INC.
- Ramakanth Alapati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Processing oven
- Patent number 11,296,049
- Issue date Apr 5, 2022
- YIELD ENGINEERING SYSTEMS, INC.
- Christopher Lane
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,843,332
- Issue date Dec 12, 2017
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,660,630
- Issue date May 23, 2017
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for transporting and processing substrates
- Patent number 9,524,896
- Issue date Dec 20, 2016
- Brooks Automation Inc.
- Terry Bluck
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,503,057
- Issue date Nov 22, 2016
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock grid for integrated circuit
- Patent number 9,473,112
- Issue date Oct 18, 2016
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with programmable overdrive capabilities
- Patent number 9,444,460
- Issue date Sep 13, 2016
- Altera Corporation
- Christopher F. Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with backside power delivery
- Patent number 9,331,062
- Issue date May 3, 2016
- Altera Corporation
- Christopher F. Lane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit floorplans
- Patent number 9,219,483
- Issue date Dec 22, 2015
- Altera Corporation
- Christopher F. Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 9,094,014
- Issue date Jul 28, 2015
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Load lock chamber designs for high-throughput processing system
- Patent number 9,022,715
- Issue date May 5, 2015
- Applied Materials, Inc.
- Alexander S. Polyak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Skewed partial column input/output floorplan
- Patent number 8,791,573
- Issue date Jul 29, 2014
- Altera Corporation
- Hui Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for power management in integrated circuits
- Patent number 8,732,635
- Issue date May 20, 2014
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,732,646
- Issue date May 20, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,407,649
- Issue date Mar 26, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for transporting and processing substrates
- Patent number 8,303,764
- Issue date Nov 6, 2012
- Brooks Automation, Inc.
- Terry Bluck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for transporting and processing substrates
- Patent number 8,293,066
- Issue date Oct 23, 2012
- Brooks Automation, Inc.
- Terry Bluck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible RAM clock enable
- Patent number 8,271,821
- Issue date Sep 18, 2012
- Altera Corporation
- Jinyong Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,201,129
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 8,198,914
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 8,191,025
- Issue date May 29, 2012
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for optimizing the performance of programmabl...
- Patent number 8,103,975
- Issue date Jan 24, 2012
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for adjusting performance of programmable log...
- Patent number 7,936,184
- Issue date May 3, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for transporting and processing substrates
- Patent number 7,901,539
- Issue date Mar 8, 2011
- Intevac, Inc.
- Terry Bluck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Versatile logic element and logic array block
- Patent number 7,671,626
- Issue date Mar 2, 2010
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundancy structures and methods in a programmable logic device
- Patent number 7,644,386
- Issue date Jan 5, 2010
- Altera Corporation
- Michael Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods of reducing power in programmable logic devices using low v...
- Patent number 7,639,042
- Issue date Dec 29, 2009
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with redundancy
- Patent number 7,589,552
- Issue date Sep 15, 2009
- Altera Corporation
- Mario E. Guzman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for processing a wafer
- Patent number 7,585,686
- Issue date Sep 8, 2009
- Applied Materials, Inc.
- Steven Verhaverbeke
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DUAL CHANNEL FLOW PLATE FOR WET PROCESSING
- Publication number 20250038013
- Publication date Jan 30, 2025
- Yield Engineering Systems, Inc.
- Vladimir Kudriavtsev
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
COATING REMOVAL APPARATUS AND METHOD
- Publication number 20240181590
- Publication date Jun 6, 2024
- Yield Engineering Systems, Inc.
- Alan Lee Stone
- B24 - GRINDING POLISHING
Information Patent Application
PLATE GAS HEATER
- Publication number 20240153793
- Publication date May 9, 2024
- Yield Engineering Systems, Inc.
- Craig W McCoy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS CHAMBER WITH UV IRRADIANCE
- Publication number 20230294190
- Publication date Sep 21, 2023
- Yield Engineering Systems, Inc.
- Tapani Laaksonen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
BATCH PROCESSING OVEN FOR MAGNETIC ANNEAL
- Publication number 20230117184
- Publication date Apr 20, 2023
- Yield Engineering Systems, Inc.
- M. Ziaul Karim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHAPING OF CONTACT STRUCTURES FOR SEMICONDUCTOR TEST, AND ASSOCIATE...
- Publication number 20170023617
- Publication date Jan 26, 2017
- TRANSLARITY, INC.
- Jens Ruffler
- G01 - MEASURING TESTING
Information Patent Application
LOST MOTION GASKET FOR SEMICONDUCTOR TEST, AND ASSOCIATED SYSTEMS A...
- Publication number 20170023642
- Publication date Jan 26, 2017
- TRANSLARITY, INC.
- Douglas A. Preston
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS FOR GENERATING AND PRESERVING VACUUM BETWEEN SE...
- Publication number 20170016954
- Publication date Jan 19, 2017
- TRANSLARITY, INC.
- Nikolai Kalnin
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20140258956
- Publication date Sep 11, 2014
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20140210515
- Publication date Jul 31, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOAD LOCK CHAMBER DESIGNS FOR HIGH-THROUGHPUT PROCESSING SYSTEM
- Publication number 20140079514
- Publication date Mar 20, 2014
- Alexander S. POLYAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20130214815
- Publication date Aug 22, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADVANCED PLATFORM FOR PASSIVATING CRYSTALLINE SILICON SOLAR CELLS
- Publication number 20130171757
- Publication date Jul 4, 2013
- HARI K. PONNEKANTI
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20120217998
- Publication date Aug 30, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and Methods for Optimizing the Performance of Programmabl...
- Publication number 20120089958
- Publication date Apr 12, 2012
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for adjusting performance of programmable log...
- Publication number 20110204919
- Publication date Aug 25, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR TRANSPORTING AND PROCESSING SUBSTRATES
- Publication number 20110158773
- Publication date Jun 30, 2011
- INTEVAC, INC.
- Terry Bluck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20090224800
- Publication date Sep 10, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR TRANSPORTING AND PROCESSING SUBSTRATES
- Publication number 20090191030
- Publication date Jul 30, 2009
- INTEVAC, INC.
- Terry Bluck
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Methods of reducing power in programmable devices using low voltage...
- Publication number 20090146688
- Publication date Jun 11, 2009
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR TRANSPORTING AND PROCESSING SUBSTRATES
- Publication number 20090078374
- Publication date Mar 26, 2009
- INTEVAC, INC.
- Terry Bluck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for processing a wafer
- Publication number 20080286697
- Publication date Nov 20, 2008
- Steven Verhaverbeke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS FOR OPTIMIZING THE PERFORMANCE OF PROGRAMMABL...
- Publication number 20080263490
- Publication date Oct 23, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20080263481
- Publication date Oct 23, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible RAM Clock Enable
- Publication number 20080253220
- Publication date Oct 16, 2008
- Altera Corporation
- Jinyong Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for processing a wafer
- Publication number 20080145797
- Publication date Jun 19, 2008
- Steven Verha Verbeke
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and apparatus for processing a wafer
- Publication number 20080138917
- Publication date Jun 12, 2008
- STEVEN VERHAVERBEKE
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and apparatus for processing a wafer
- Publication number 20080085477
- Publication date Apr 10, 2008
- Steven Verhaverbeke
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Apparatus and methods for transporting and processing substrates
- Publication number 20080066678
- Publication date Mar 20, 2008
- INTEVAC INC.
- Terry Bluck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK
- Publication number 20070252617
- Publication date Nov 1, 2007
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY

Christopher Lane

Person

Patents Grantslast 30 patents

Dielectric liners on through glass vias

Processing oven

Clock grid for integrated circuit

Clock grid for integrated circuit

Apparatus and methods for transporting and processing substrates

Clock grid for integrated circuit

Clock grid for integrated circuit

Integrated circuits with programmable overdrive capabilities

Integrated circuits with backside power delivery

Integrated circuit floorplans

PLD architecture for flexible placement of IP function blocks

Load lock chamber designs for high-throughput processing system

Skewed partial column input/output floorplan

Apparatus and methods for power management in integrated circuits

PLD architecture for flexible placement of IP function blocks

PLD architecture for flexible placement of IP function blocks

Apparatus and methods for transporting and processing substrates

Apparatus and methods for transporting and processing substrates

Flexible RAM clock enable

PLD architecture for flexible placement of IP function blocks

Apparatus and methods for adjusting performance of programmable log...

Redundancy structures and methods in a programmable logic device

Apparatus and methods for optimizing the performance of programmabl...

Apparatus and methods for adjusting performance of programmable log...

Apparatus and methods for transporting and processing substrates

Versatile logic element and logic array block

Redundancy structures and methods in a programmable logic device

Methods of reducing power in programmable logic devices using low v...

Integrated circuit with redundancy

Method and apparatus for processing a wafer

Patents Applicationslast 30 patents

DUAL CHANNEL FLOW PLATE FOR WET PROCESSING

COATING REMOVAL APPARATUS AND METHOD

PLATE GAS HEATER

PROCESS CHAMBER WITH UV IRRADIANCE

BATCH PROCESSING OVEN FOR MAGNETIC ANNEAL

SHAPING OF CONTACT STRUCTURES FOR SEMICONDUCTOR TEST, AND ASSOCIATE...

LOST MOTION GASKET FOR SEMICONDUCTOR TEST, AND ASSOCIATED SYSTEMS A...

SYSTEMS AND METHODS FOR GENERATING AND PRESERVING VACUUM BETWEEN SE...

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

LOAD LOCK CHAMBER DESIGNS FOR HIGH-THROUGHPUT PROCESSING SYSTEM

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

ADVANCED PLATFORM FOR PASSIVATING CRYSTALLINE SILICON SOLAR CELLS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Apparatus and Methods for Optimizing the Performance of Programmabl...

Apparatus and methods for adjusting performance of programmable log...

APPARATUS AND METHODS FOR TRANSPORTING AND PROCESSING SUBSTRATES

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

APPARATUS AND METHODS FOR TRANSPORTING AND PROCESSING SUBSTRATES

Methods of reducing power in programmable devices using low voltage...

APPARATUS AND METHODS FOR TRANSPORTING AND PROCESSING SUBSTRATES

Method and apparatus for processing a wafer

APPARATUS AND METHODS FOR OPTIMIZING THE PERFORMANCE OF PROGRAMMABL...

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

Flexible RAM Clock Enable

Method and apparatus for processing a wafer

Method and apparatus for processing a wafer

Method and apparatus for processing a wafer

Apparatus and methods for transporting and processing substrates

VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK