Christopher S. Johnson

Person

Meridian, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Defective memory cell detection circuitry including use in automoti...
- Patent number 10,832,793
- Issue date Nov 10, 2020
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for selective determination of data error r...
- Patent number 10,437,669
- Issue date Oct 8, 2019
- Micron Technology, Inc.
- Ryan S. Laity
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for selective determination of data error r...
- Patent number 9,934,086
- Issue date Apr 3, 2018
- Micron Technology, Inc.
- Ryan S. Laity
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting communication errors on a bus
- Patent number 8,739,011
- Issue date May 27, 2014
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable byte lane offset for memory module to reduce skew
- Patent number 8,631,267
- Issue date Jan 14, 2014
- Mircon Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting communication errors on a bus
- Patent number 8,489,975
- Issue date Jul 16, 2013
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting communication errors on a bus
- Patent number 8,296,639
- Issue date Oct 23, 2012
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically setting burst length of double data rate memory device...
- Patent number 8,281,052
- Issue date Oct 2, 2012
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method having low-power, high write latency mode...
- Patent number 8,164,965
- Issue date Apr 24, 2012
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically setting burst length of double data rate memory device...
- Patent number 8,156,262
- Issue date Apr 10, 2012
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting communication errors on a bus
- Patent number 8,074,159
- Issue date Dec 6, 2011
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable byte lane offset for memory module to reduce skew
- Patent number 8,065,551
- Issue date Nov 22, 2011
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically setting burst length of double data rate memory device...
- Patent number 8,019,913
- Issue date Sep 13, 2011
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
User selectable banks for DRAM
- Patent number 7,995,420
- Issue date Aug 9, 2011
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically setting burst length of double data rate memory device...
- Patent number 7,984,207
- Issue date Jul 19, 2011
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method having low-power, high write latency mode...
- Patent number 7,826,283
- Issue date Nov 2, 2010
- Round Rock Research, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting communication errors on a bus
- Patent number 7,747,933
- Issue date Jun 29, 2010
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User selectable banks for DRAM
- Patent number 7,636,271
- Issue date Dec 22, 2009
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically setting burst length of memory device by applying signa...
- Patent number 7,603,493
- Issue date Oct 13, 2009
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjustable byte lane offset for memory module to reduce skew
- Patent number 7,457,978
- Issue date Nov 25, 2008
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method having low-power, high write latency mode...
- Patent number 7,450,447
- Issue date Nov 11, 2008
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method having low-power, high write latency mode...
- Patent number 7,254,067
- Issue date Aug 7, 2007
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling multiple signal polarity in a semiconductor device
- Patent number 7,215,582
- Issue date May 8, 2007
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
User selectable banks for DRAM
- Patent number 7,203,122
- Issue date Apr 10, 2007
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling multiple signal polarity in a semiconductor device
- Patent number 7,177,224
- Issue date Feb 13, 2007
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectable clock input
- Patent number 7,177,231
- Issue date Feb 13, 2007
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method having low-power, high write latency mode...
- Patent number 7,149,141
- Issue date Dec 12, 2006
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically setting burst length of memory device by applying signa...
- Patent number 7,149,824
- Issue date Dec 12, 2006
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous DRAM with selectable internal prefetch size
- Patent number 7,120,754
- Issue date Oct 10, 2006
- Micron Technology, Inc.
- Kevin J. Ryan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method having low-power, high write latency mode...
- Patent number 7,027,337
- Issue date Apr 11, 2006
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DEFECTIVE MEMORY CELL DETECTION CIRCUITRY INCLUDING USE IN AUTOMOTI...
- Publication number 20200066368
- Publication date Feb 27, 2020
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR SELECTIVE DETERMINATION OF DATA ERROR R...
- Publication number 20180181464
- Publication date Jun 28, 2018
- Micron Technology, Inc.
- Ryan S. Laity
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR SELECTIVE DETERMINATION OF DATA ERROR R...
- Publication number 20170351570
- Publication date Dec 7, 2017
- Micron Technology, Inc.
- Ryan S. Laity
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adjustable Byte Lane Offset For Memory Module to Reduce Skew
- Publication number 20140129869
- Publication date May 8, 2014
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS
- Publication number 20130305128
- Publication date Nov 14, 2013
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS
- Publication number 20130013985
- Publication date Jan 10, 2013
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE...
- Publication number 20120198144
- Publication date Aug 2, 2012
- ROUND ROCK RESEARCH, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS
- Publication number 20120079358
- Publication date Mar 29, 2012
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adjustable Byte Lane Offset For Memory Module to Reduce Skew
- Publication number 20120047388
- Publication date Feb 23, 2012
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE...
- Publication number 20120005420
- Publication date Jan 5, 2012
- ROUND ROCK RESEARCH, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE...
- Publication number 20110038217
- Publication date Feb 17, 2011
- ROUND ROCK RESEARCH, LLC
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY...
- Publication number 20100332718
- Publication date Dec 30, 2010
- Micron Technology, Inc.
- Todd D. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS
- Publication number 20100262872
- Publication date Oct 14, 2010
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USER SELECTABLE BANKS FOR DRAM
- Publication number 20100097878
- Publication date Apr 22, 2010
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMICALLY SETTING BURST LENGTH OF A DOUBLE DATA RATE MEMORY DEVICE
- Publication number 20090307446
- Publication date Dec 10, 2009
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMICALLY SETTING BURST TYPE OF A DOUBLE DATA RATE MEMORY DEVICE
- Publication number 20090276548
- Publication date Nov 5, 2009
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE...
- Publication number 20090067267
- Publication date Mar 12, 2009
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Adjustable Byte Lane Offset For Memory Module To Reduce Skew
- Publication number 20090055675
- Publication date Feb 26, 2009
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory device and method having low-power, high write latency mode...
- Publication number 20070268756
- Publication date Nov 22, 2007
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Selectable clock unit
- Publication number 20070189106
- Publication date Aug 16, 2007
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for detecting communication errors on a bus
- Publication number 20070033512
- Publication date Feb 8, 2007
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling multiple signal polarity in a semiconductor device
- Publication number 20060262604
- Publication date Nov 23, 2006
- Micron Technology, Inc.
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Adjustable byte lane offset for memory module to reduce skew
- Publication number 20060253721
- Publication date Nov 9, 2006
- Micron Technology, Inc.
- Christopher S. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory device and method having low-power, high write latency mode...
- Publication number 20060152983
- Publication date Jul 13, 2006
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronous DRAM with selectable internal prefetch size
- Publication number 20060112231
- Publication date May 25, 2006
- Micron Technology, Inc.
- Kevin J. Ryan
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamically setting burst length and type
- Publication number 20060090056
- Publication date Apr 27, 2006
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Selectable clock input
- Publication number 20060062056
- Publication date Mar 23, 2006
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and method having low-power, high write latency mode...
- Publication number 20050122797
- Publication date Jun 9, 2005
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and method having low-power, high write latency mode...
- Publication number 20050117414
- Publication date Jun 2, 2005
- Christopher S. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronous DRAM with selectable internal prefetch size
- Publication number 20050083758
- Publication date Apr 21, 2005
- Kevin J. Ryan
- G11 - INFORMATION STORAGE

Christopher S. Johnson

Person

Patents Grantslast 30 patents

Defective memory cell detection circuitry including use in automoti...

Apparatuses and methods for selective determination of data error r...

Apparatuses and methods for selective determination of data error r...

Method and apparatus for detecting communication errors on a bus

Adjustable byte lane offset for memory module to reduce skew

Method and apparatus for detecting communication errors on a bus

Method and apparatus for detecting communication errors on a bus

Dynamically setting burst length of double data rate memory device...

Memory device and method having low-power, high write latency mode...

Dynamically setting burst length of double data rate memory device...

Method and apparatus for detecting communication errors on a bus

Adjustable byte lane offset for memory module to reduce skew

Dynamically setting burst length of double data rate memory device...

User selectable banks for DRAM

Dynamically setting burst length of double data rate memory device...

Memory device and method having low-power, high write latency mode...

Method and apparatus for detecting communication errors on a bus

User selectable banks for DRAM

Dynamically setting burst length of memory device by applying signa...

Adjustable byte lane offset for memory module to reduce skew

Memory device and method having low-power, high write latency mode...

Memory device and method having low-power, high write latency mode...

Controlling multiple signal polarity in a semiconductor device

User selectable banks for DRAM

Controlling multiple signal polarity in a semiconductor device

Selectable clock input

Memory device and method having low-power, high write latency mode...

Dynamically setting burst length of memory device by applying signa...

Synchronous DRAM with selectable internal prefetch size

Memory device and method having low-power, high write latency mode...

Patents Applicationslast 30 patents

DEFECTIVE MEMORY CELL DETECTION CIRCUITRY INCLUDING USE IN AUTOMOTI...

APPARATUSES AND METHODS FOR SELECTIVE DETERMINATION OF DATA ERROR R...

APPARATUSES AND METHODS FOR SELECTIVE DETERMINATION OF DATA ERROR R...

Adjustable Byte Lane Offset For Memory Module to Reduce Skew

METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS

METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS

DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE...

METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS

Adjustable Byte Lane Offset For Memory Module to Reduce Skew

DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE...

MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE...

SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY...

METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS

USER SELECTABLE BANKS FOR DRAM

DYNAMICALLY SETTING BURST LENGTH OF A DOUBLE DATA RATE MEMORY DEVICE

DYNAMICALLY SETTING BURST TYPE OF A DOUBLE DATA RATE MEMORY DEVICE

MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE...

Adjustable Byte Lane Offset For Memory Module To Reduce Skew

Memory device and method having low-power, high write latency mode...

Selectable clock unit

Method and apparatus for detecting communication errors on a bus

Controlling multiple signal polarity in a semiconductor device

Adjustable byte lane offset for memory module to reduce skew

Memory device and method having low-power, high write latency mode...

Synchronous DRAM with selectable internal prefetch size

Dynamically setting burst length and type

Selectable clock input

Memory device and method having low-power, high write latency mode...

Memory device and method having low-power, high write latency mode...

Synchronous DRAM with selectable internal prefetch size