Chu-Cheow Lim

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-use package architecture
- Patent number 11,929,295
- Issue date Mar 12, 2024
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimal selection of compression entries for compressing program in...
- Patent number 7,688,232
- Issue date Mar 30, 2010
- Intel Corporation
- Chu-Cheow Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to optimize speculative parallel threading
- Patent number 7,627,864
- Issue date Dec 1, 2009
- Intel Corporation
- Zhao Hui Du
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource-aware scheduling for compilers
- Patent number 7,617,495
- Issue date Nov 10, 2009
- Intel Corporation
- Kalyan Muthukumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computation of all-pairs reaching probabilities in software systems
- Patent number 7,379,858
- Issue date May 27, 2008
- Intel Corporation
- Chu-Cheow Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alias-free test for dynamic array structures
- Patent number 6,880,154
- Issue date Apr 12, 2005
- Intel Corporation
- Somnath Ghosh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED INDUCTOR OVER TRANSISTOR LAYER
- Publication number 20240234303
- Publication date Jul 11, 2024
- Intel Corporation
- Min Suet LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED INDUCTOR OVER TRANSISTOR LAYER
- Publication number 20240136279
- Publication date Apr 25, 2024
- Intel Corporation
- Min Suet LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE
- Publication number 20240006336
- Publication date Jan 4, 2024
- Intel Corporation
- Telesphor KAMGAING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE
- Publication number 20230420354
- Publication date Dec 28, 2023
- Intel Corporation
- Telesphor KAMGAING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SE...
- Publication number 20230420350
- Publication date Dec 28, 2023
- Intel Corporation
- Kavitha NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE
- Publication number 20230420384
- Publication date Dec 28, 2023
- Intel Corporation
- Kavitha NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES
- Publication number 20230420345
- Publication date Dec 28, 2023
- Intel Corporation
- Kavitha NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ON PACKAGE (MOP) ARCHITECTURE
- Publication number 20230395576
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON PACKAGE INTERCONNECT ARCHITECTURE FOR HIGH-SPEED MEMORY
- Publication number 20230395493
- Publication date Dec 7, 2023
- Intel Corporation
- Jooi Wah WONG
- G11 - INFORMATION STORAGE
Information Patent Application
EMI CAGE FOR MICROSTRIP ROUTING VIA DUAL LAYER UNDERFILL CONCEPT
- Publication number 20230395524
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-LASER THOUGH HOLE (ULTH) BY MULTI-STACKED CORE CONCEPT
- Publication number 20230397333
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MEMORY PACKAGE ON EXTENDED BASE DIE OVER SOC DIE FOR PACKAGE LAYER...
- Publication number 20230395578
- Publication date Dec 7, 2023
- Intel Corporation
- Min Suet LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOC-MEMORY INTEGRATION TO ACHIEVE SMALLEST AND THINNEST MEMORY ON P...
- Publication number 20230395577
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES WITH ON PACKAGE MEMORY ARCHITECTURES
- Publication number 20230091395
- Publication date Mar 23, 2023
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-USE PACKAGE ARCHITECTURE
- Publication number 20220181227
- Publication date Jun 9, 2022
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STEPPED PACKAGE AND RECESSED CIRCUIT BOARD
- Publication number 20220110214
- Publication date Apr 7, 2022
- Intel Corporation
- Martin M. Chang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEM AND METHOD FOR STACKING WIRE-BOND CONVERTED FLIP-CHIP DIE
- Publication number 20210202441
- Publication date Jul 1, 2021
- Intel Corporation
- ENG HUAT GOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-USE PACKAGE ARCHITECTURE
- Publication number 20190287872
- Publication date Sep 19, 2019
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTIMAL SELECTION OF COMPRESSION ENTRIES FOR COMPRESSING PROGRAM IN...
- Publication number 20080244245
- Publication date Oct 2, 2008
- Chu-Cheow Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for compaction and/or decompaction
- Publication number 20080162522
- Publication date Jul 3, 2008
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to optimize speculative parallel threading
- Publication number 20070011684
- Publication date Jan 11, 2007
- Zhao Hui Du
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource-aware scheduling for compilers
- Publication number 20050216899
- Publication date Sep 29, 2005
- Kalyan Muthukumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computation of all-pairs reaching probabilities in software systems
- Publication number 20050182602
- Publication date Aug 18, 2005
- Intel Corporation
- Chu-Cheow Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Alias-free test for dynamic array structures
- Publication number 20030005420
- Publication date Jan 2, 2003
- Somnath Ghosh
- G06 - COMPUTING CALCULATING COUNTING

Chu-Cheow Lim

Person

Patents Grantslast 30 patents

Multi-use package architecture

Optimal selection of compression entries for compressing program in...

Mechanism to optimize speculative parallel threading

Resource-aware scheduling for compilers

Computation of all-pairs reaching probabilities in software systems

Alias-free test for dynamic array structures

Patents Applicationslast 30 patents

INTEGRATED INDUCTOR OVER TRANSISTOR LAYER

INTEGRATED INDUCTOR OVER TRANSISTOR LAYER

SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE

ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE

HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SE...

SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE

COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES

MEMORY ON PACKAGE (MOP) ARCHITECTURE

ON PACKAGE INTERCONNECT ARCHITECTURE FOR HIGH-SPEED MEMORY

EMI CAGE FOR MICROSTRIP ROUTING VIA DUAL LAYER UNDERFILL CONCEPT

ULTRA-LASER THOUGH HOLE (ULTH) BY MULTI-STACKED CORE CONCEPT

MEMORY PACKAGE ON EXTENDED BASE DIE OVER SOC DIE FOR PACKAGE LAYER...

SOC-MEMORY INTEGRATION TO ACHIEVE SMALLEST AND THINNEST MEMORY ON P...

INTEGRATED CIRCUIT PACKAGES WITH ON PACKAGE MEMORY ARCHITECTURES

MULTI-USE PACKAGE ARCHITECTURE

STEPPED PACKAGE AND RECESSED CIRCUIT BOARD

SYSTEM AND METHOD FOR STACKING WIRE-BOND CONVERTED FLIP-CHIP DIE

MULTI-USE PACKAGE ARCHITECTURE

OPTIMAL SELECTION OF COMPRESSION ENTRIES FOR COMPRESSING PROGRAM IN...

Methods and apparatuses for compaction and/or decompaction

Mechanism to optimize speculative parallel threading

Resource-aware scheduling for compilers

Computation of all-pairs reaching probabilities in software systems

Alias-free test for dynamic array structures