Patent Application
20210202441
Analog and/or digital circuits may be created on substrates made of silicon or other materials; these substrates may be placed in a package for durability, reliability, or other similar reasons. In order to communicate with other circuits and/or systems, the package may include one or more conductors that electrically connect an input and/or output signal in the circuit within the package to the package exterior to thereby permit the other circuits and/or systems to send and receive electrical signals to the circuit within the package. The package may further include conductors that supply power to the circuit within the package or any other type of conductor.
Conductors in a package may be wire-bond conductors in which a metal pad on the substrate is wire-bonded to a pin on the package, allowing other circuits and/or systems to send and/or receive signals to any circuit disposed on the substrate connected to the metal pad. Wire-bond conductors may be simple and/or cheap to produce and manufacture, but they have disadvantages including parasitic inductance that may limit the signal frequency and/or edge rate they can support. The conductors may instead be bumps on the substrate that, when the substrate is flipped over, connect directly to another substrate or other circuit or system. Large numbers of these “flip-chip” substrates may, however, consume an unacceptably high amount of system real estate.
In various embodiments, two or more dies are stacked on top of each other and disposed on and in electrical communication with a system substrate. The dies may include a substrate made of a semiconductor material, such as silicon, and transistors, resistors, insulators, conductors, and/or other components formed in or on the substrate to form digital and/or analog logic. The system substrate may be another substrate, a motherboard, or any other such device. The dies may include any circuit, memory, storage, or any other device; in some embodiments, the dies are memory components such as low-power double data rate 3 (“LPDDR3”) dynamic random-access memory (“DRAM”). The system substrate may similarly include any circuit, memory, storage, or any other device. A set of metal columns electrically connects each die with the system substrate. A first set of metal columns having a first height of, for example, 18 microns, connects a first die to the system substrate; solder bumps may be used to connect to connect the metal columns to the first die and/or system substrate. The first die may have a thickness of 15-20 microns; in some embodiments, the thickness of the first die is 18 microns. A second die is disposed at least partially on top of the first die such that at least a portion of the first die is disposed between the second die and the system substrate. A second set of metal columns having a second height of, for example, 90-120 microns, connects the second die to the system substrate; solder bumps may be used to connect to connect the metal columns to the second die and/or system substrate. An adhesive film may be used to connect the first and second die, and an underfill layer may be added between the first die and the system substrate. Stacking the dies in accordance with the embodiments disclosed herein may allow a 40-50% reduction in the area required on the system substrate for the dies, as compared to unstacked dies.
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In various embodiments, an electronic assembly comprising a system substrate may communicate electronically with a first (i.e., lower-stack) die and a second (i.e., upper-stack die). The system substrate may transmit a first signal through a first set of first metal columns having a first height on a first die and transmit a second signal through a second set of second metal columns having a second height greater than the first height on a second die. At least a portion of the first die may be disposed between the second die and the system substrate, as described above.
Example 1 is an electronic assembly comprising a system substrate; a first die disposed on and in electrical communication with the system substrate using a first set of first metal columns having a first height; a second die disposed on and in electrical communication with the system substrate using a second set of second metal columns having a second height greater than the first height such that at least a portion of the first die is disposed between the second die and the system substrate.
Example 2 includes the subject matter of example 1, further comprising an adhesive film disposed between the first die and the second die.
Example 3 includes the subject matter of example 1, where the first die comprises a flip-chip die and the second die comprising a flip-chip die.
Example 4 includes the subject matter of example 1, the first die comprising a converted wire-bond die and the second die comprising a converted wire-bond die.
Example 5 includes the subject matter of example 1, further comprising a third die disposed on and in electrical communication with the system substrate using a third set of third metal columns having a third height such that at least a portion of the third die is disposed between the second die and the system substrate.
Example 6 includes the subject matter of example 1, where a portion of the first die extend beyond a perimeter of the second die.
Example 7 includes the subject matter of example 1, the first die comprising a dynamic random-access memory.
Example 8 includes the subject matter of example 1, further comprising an underfill layer disposed between the first die and the system substrate.
Example 9 includes the subject matter of example 1, where the first metal columns comprise copper.
Example 10 includes the subject matter of example 1, where the first metal columns comprise a solder bump.
Example 11 includes the subject matter of example 1, where the first height comprises 15-20 microns.
Example 12 includes the subject matter of example 11, where the first height comprises 18 microns.
Example 13 includes the subject matter of example 1, where the second height comprises 90-120 microns.
Example 14 includes the subject matter of example 13, where the second height comprises 90 microns.
Example 15 includes the subject matter of example 1, where a thickness of the first die comprises 50 microns.
Example 16 includes the subject matter of example 1, where a thickness of the second die comprises 300 microns.
Example 17 is a method for forming an electronic assembly, the method comprising forming a first set of first metal columns having a first height on a first die; forming a second set of second metal columns having a second height greater than the first height on a second die; depositing an adhesive film on a surface of the second die; attaching a surface of the first die to the adhesive film; thermo-compression bonding the first metal columns and second metal columns to a system substrate.
Example 18 includes the subject matter of example 17, further comprising depositing an underfill layer between the second die and the system substrate.
Example 19 includes the subject matter of example 17, further comprising depositing solder bumps on the first columns and second columns
Example 20 includes the subject matter of example 17, further comprising converting the first die from a wire-bond die to a flip-chip die.
Example 21 includes the subject matter of example 17, further comprising forming the first die to have a thickness comprising 50 microns.
Example 22 includes the subject matter of example 17, further comprising forming the second die to have a thickness comprising 300 microns.
Example 23 includes the subject matter of example 17, where the first height comprises 15-20 microns.
Example 24 includes the subject matter of example 23, where the first height comprises 18 microns.
Example 25 includes the subject matter of example 17, where the second height comprises 90-120 microns.
Example 26 includes the subject matter of example 25, where the second height comprises 90 microns.
Example 27 is a method for electronically communicating with circuits disposed on a plurality of dies, the method comprising transmitting a first signal from a system substrate through a first set of first metal columns electrically connected to the system substrate and having a first height to a first die electrically connected to the first set of first metal columns; transmitting a second signal from a system substrate through a second set of second metal columns electrically connected to the system substrate and having a second height greater than the first height to a second die electrically connected to the second set of second metal columns, at least a portion of the first die being disposed between the second die and the system substrate.
Example 28 includes the subject matter of example 27, further comprising depositing an underfill layer between the second die and the system substrate.
Example 29 includes the subject matter of example 27, further comprising depositing solder bumps on the first columns and second columns.
Example 30 includes the subject matter of example 27, further comprising converting the first die from a wire-bond die to a flip-chip die.
Example 31 includes the subject matter of example 27, further comprising forming the first die to have a thickness comprising 50 microns.
Example 32 includes the subject matter of example 27, further comprising forming the second die to have a thickness comprising 300 microns.
Example 33 includes the subject matter of example 27, where the first die comprises a dynamic random-access memory.
Example 34 includes the subject matter of example 27, where the first metal columns comprise copper.
Example 35 includes the subject matter of example 27, where the first metal columns comprise a solder bump.
Some embodiments may be described using the expression “one embodiment” or “an embodiment” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Further, some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and/or “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
It is emphasized that the Abstract of the Disclosure is provided to allow a reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “including” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.
What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and/or methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2016/016881 | 2/5/2016 | WO | 00 |
