Chulwoo Kim

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Circuit and related method for synchronizing data signals to a core...
- Patent number 7,698,588
- Issue date Apr 13, 2010
- International Business Machines Corporation
- David William Boerstler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
CMOS parallel dynamic logic and speed enhanced static logic
- Patent number 6,794,903
- Issue date Sep 21, 2004
- The Board of Trustees of the University of Illinois
- Chulwoo Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop clock generator
- Patent number 6,784,707
- Issue date Aug 31, 2004
- The Board of Trustees of the University of Illinois
- Chulwoo Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS sequential logic configuration for an edge triggered flip-flop
- Patent number 6,784,694
- Issue date Aug 31, 2004
- The Board of Trustees of the University of Illinois
- Chulwoo Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS skewed static logic and method of synthesis
- Patent number 6,624,665
- Issue date Sep 23, 2003
- The Board of Trustees of the University of Illinois
- Chulwoo Kim
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Circuit and related method for synchronizing data signals to a core...
- Publication number 20050018799
- Publication date Jan 27, 2005
- International Business Machines Corporation
- David William Boerstler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Delay locked loop clock generator
- Publication number 20040008063
- Publication date Jan 15, 2004
- The Board of trustees of the University of Illinois
- Chulwoo Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CMOS sequential logic configuration for an edge triggered flip-flop
- Publication number 20030052716
- Publication date Mar 20, 2003
- The Board of trustees of the University of Illinois
- Chulwoo Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CMOS parallel dynamic logic and speed enhanced skewed state logic
- Publication number 20020190756
- Publication date Dec 19, 2002
- The Board of Trustees of the University of Illinoi
- Chulwoo Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS skewed static logic and method of synthesis
- Publication number 20020175712
- Publication date Nov 28, 2002
- The Board of trustees of the University of Illinois
- Chulwoo Kim
- H03 - BASIC ELECTRONIC CIRCUITRY