Coralyn S. Gauvin

Person

Manitou Sorings, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Classifying bit errors in transmitted run length limited data
- Patent number 9,267,991
- Issue date Feb 23, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Coralyn S. Gauvin
- G01 - MEASURING TESTING
Information Patent Grant
Classifying bit errors in transmitted run length limited data
- Patent number 9,021,325
- Issue date Apr 28, 2015
- LSI Corporation
- Coralyn S. Gauvin
- G01 - MEASURING TESTING
Information Patent Grant
Data path utilization for low level pattern generation and checkiing
- Patent number 8,854,983
- Issue date Oct 7, 2014
- LSI Corporation
- Gabriel L. Romero
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Complex pattern generator for analysis of high speed serial streams
- Patent number 7,774,669
- Issue date Aug 10, 2010
- LSI Corporation
- Gabriel L. Romero
- G01 - MEASURING TESTING
Information Patent Grant
Self verifying communications testing
- Patent number 7,409,618
- Issue date Aug 5, 2008
- LSI Corporation
- Gabriel Romero
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Routing of test signals of integrated circuits
- Patent number 7,114,135
- Issue date Sep 26, 2006
- LSI Logic Corporation
- Coralyn S. Gauvin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for efficient layout of functionally extraneous c...
- Patent number 6,470,484
- Issue date Oct 22, 2002
- LSI Logic Corporation
- Brian A. Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IO power management: synchronously regulated output skew
- Patent number 6,459,313
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Joy F. Godbee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual path asynchronous delay circuit
- Patent number 6,255,878
- Issue date Jul 3, 2001
- LSI Logic Corporation
- Coralyn S. Gauvin
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA
- Publication number 20150205653
- Publication date Jul 23, 2015
- Avago Technologies Limited
- Coralyn S. Gauvin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA
- Publication number 20140223270
- Publication date Aug 7, 2014
- LSI Corporation
- Coralyn S. Gauvin
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR ANALYZING DIFFERENT SIGNALING PATHWAYS TH...
- Publication number 20140052404
- Publication date Feb 20, 2014
- LSI Corporation
- Coralyn S. Gauvin
- G01 - MEASURING TESTING
Information Patent Application
DATA PATH UTILIZATION FOR LOW LEVEL PATTERN GENERATION AND CHECKIING
- Publication number 20120140840
- Publication date Jun 7, 2012
- LSI Corporation
- Gabriel L. Romero
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Peak Detector Extension System
- Publication number 20120119789
- Publication date May 17, 2012
- LSI Corporation
- Gabriel Leandro Romero
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS FOR INTERCONNECTING SAS/SATA DEVICES USING EI...
- Publication number 20110106997
- Publication date May 5, 2011
- LSI Corporation
- Gabriel L. Romero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Complex Pattern Generator for Analysis of High Speed Serial Streams
- Publication number 20080307283
- Publication date Dec 11, 2008
- Gabriel L. Romero
- G01 - MEASURING TESTING
Information Patent Application
Self verifying communications testing
- Publication number 20060075318
- Publication date Apr 6, 2006
- LSI Logic Corporation
- Gabriel Romero
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Mapping test mux structure
- Publication number 20050044460
- Publication date Feb 24, 2005
- Timothy E. Hoglund
- G01 - MEASURING TESTING

Coralyn S. Gauvin

Person

Patents Grantslast 30 patents

Classifying bit errors in transmitted run length limited data

Classifying bit errors in transmitted run length limited data

Data path utilization for low level pattern generation and checkiing

Complex pattern generator for analysis of high speed serial streams

Self verifying communications testing

Routing of test signals of integrated circuits

System and method for efficient layout of functionally extraneous c...

IO power management: synchronously regulated output skew

Dual path asynchronous delay circuit

Patents Applicationslast 30 patents

CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA

CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA

METHODS AND STRUCTURE FOR ANALYZING DIFFERENT SIGNALING PATHWAYS TH...

DATA PATH UTILIZATION FOR LOW LEVEL PATTERN GENERATION AND CHECKIING

Peak Detector Extension System

METHODS AND APPARATUS FOR INTERCONNECTING SAS/SATA DEVICES USING EI...

Complex Pattern Generator for Analysis of High Speed Serial Streams

Self verifying communications testing

Mapping test mux structure