Corvin Liaw

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Method for operating an integrated circuit having a resistivity cha...
- Patent number 8,531,863
- Issue date Sep 10, 2013
- Adesto Technologies Corporation
- Ralf Symanczyk
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of determining a memory state of a resistive memory cell and...
- Patent number 7,869,253
- Issue date Jan 11, 2011
- Qimonda AG
- Corvin Liaw
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integrated circuit with Resistivity changing memory cells and metho...
- Patent number 7,706,201
- Issue date Apr 27, 2010
- Qimonda AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit including a resistive memory element and method for...
- Patent number 7,599,209
- Issue date Oct 6, 2009
- Infineon Technologies AG
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory arrangement
- Patent number 7,561,460
- Issue date Jul 14, 2009
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit, method for operating a memory circuit, memory devic...
- Patent number 7,522,444
- Issue date Apr 21, 2009
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory device and method for writing to a resistive memor...
- Patent number 7,518,902
- Issue date Apr 14, 2009
- Infineon Technologies AG
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method for operating such a memory device
- Patent number 7,447,053
- Issue date Nov 4, 2008
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 7,440,303
- Issue date Oct 21, 2008
- Qimonda AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and memory circuit for operating a resistive memory cell
- Patent number 7,428,163
- Issue date Sep 23, 2008
- Infineon Technologies AG
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge-trapping memory device and methods for operating and manufac...
- Patent number 7,402,490
- Issue date Jul 22, 2008
- Infineon Technologies AG
- Thomas Mikolajick
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for generating a reference voltage and for reading a memory...
- Patent number 7,342,819
- Issue date Mar 11, 2008
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory device and method for operating the same
- Patent number 7,280,392
- Issue date Oct 9, 2007
- Infineon Technologies, AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory with an arrangement of nonvolatile...
- Patent number 7,277,312
- Issue date Oct 2, 2007
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bit virtual-ground NAND memory device
- Patent number 7,272,040
- Issue date Sep 18, 2007
- Infineon Technologies AG
- Thomas Mikolajick
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method for reading out a memory datum from such...
- Patent number 7,254,052
- Issue date Aug 7, 2007
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device comprising memory cells with floating g...
- Patent number 7,250,651
- Issue date Jul 31, 2007
- Infineon Technologies AG
- Karl-Heinz Küsters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive memory arrangement
- Patent number 7,215,568
- Issue date May 8, 2007
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge-trapping memory device including high permittivity strips
- Patent number 7,049,651
- Issue date May 23, 2006
- Infineon Technologies AG
- Thomas Mikolajick
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit and Method of Improved Determining a Memory Stat...
- Publication number 20090213643
- Publication date Aug 27, 2009
- Michael Angerbauer
- G11 - INFORMATION STORAGE
Information Patent Application
Method of Operating an Integrated Circuit, Integrated Circuit, and...
- Publication number 20090021976
- Publication date Jan 22, 2009
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit, Memory Module, Method of Operating an Integrate...
- Publication number 20080273369
- Publication date Nov 6, 2008
- Michael Angerbauer
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT HAVING A MEMORY ARRAY
- Publication number 20080205179
- Publication date Aug 28, 2008
- QIMONDA AG
- Michael Markert
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT
- Publication number 20080056041
- Publication date Mar 6, 2008
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and method of improving the reliability of a memory d...
- Publication number 20080043544
- Publication date Feb 21, 2008
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Method of determining a memory state of a resistive memory cell and...
- Publication number 20080043521
- Publication date Feb 21, 2008
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
INTERGRATED CIRCUIT HAVING MEMORY WITH RESISTIVE MEMORY CELLS
- Publication number 20080043513
- Publication date Feb 21, 2008
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND MEMORY CIRCUIT FOR OPERATING A RESISTIVE MEMORY CELL
- Publication number 20080019163
- Publication date Jan 24, 2008
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit, method for operating a memory circuit, memory devic...
- Publication number 20070211514
- Publication date Sep 13, 2007
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Memory Arrangement
- Publication number 20070211515
- Publication date Sep 13, 2007
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20070211528
- Publication date Sep 13, 2007
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and method for operating such a memory device
- Publication number 20070211513
- Publication date Sep 13, 2007
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Methods for generating a reference voltage and for reading a memory...
- Publication number 20070206402
- Publication date Sep 6, 2007
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit having a resistive memory cell and method for operat...
- Publication number 20070195580
- Publication date Aug 23, 2007
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
CBRAM memory device and method for writing to a resistive memory ce...
- Publication number 20070171697
- Publication date Jul 26, 2007
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit including a resistive memory element and method for...
- Publication number 20070171698
- Publication date Jul 26, 2007
- Heinz Hoenigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit as well as method for evaluating a memory datum of a...
- Publication number 20070091667
- Publication date Apr 26, 2007
- Qimonda AG
- Thomas Rohr
- G11 - INFORMATION STORAGE
Information Patent Application
Memory comprising a memory device and a write unit configured as a...
- Publication number 20070008863
- Publication date Jan 11, 2007
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Method for operating a PMC memory cell and CBRAM memory circuit
- Publication number 20060265548
- Publication date Nov 23, 2006
- Ralf Symanczyk
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-bit virtual-ground NAND memory device
- Publication number 20060245233
- Publication date Nov 2, 2006
- Thomas Mikolajick
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory with an arrangement of nonvolatile...
- Publication number 20060187701
- Publication date Aug 24, 2006
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory device and method for operating the same
- Publication number 20060168505
- Publication date Jul 27, 2006
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit and method for reading out a memory datum from such...
- Publication number 20060126413
- Publication date Jun 15, 2006
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory with volatile and non-volatile memory cells
- Publication number 20060120138
- Publication date Jun 8, 2006
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Charge-trapping memory device and methods for operating and manufac...
- Publication number 20060091448
- Publication date May 4, 2006
- Thomas Mikolajick
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive memory arrangement
- Publication number 20060050547
- Publication date Mar 9, 2006
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device comprising memory cells with floating g...
- Publication number 20060038220
- Publication date Feb 23, 2006
- Karl-Heinz Kusters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Charge-trapping memory device and methods for operating and manufac...
- Publication number 20050104117
- Publication date May 19, 2005
- Thomas Mikolajick
- G11 - INFORMATION STORAGE

Corvin Liaw

Person

Patents Grantslast 30 patents

Method for operating an integrated circuit having a resistivity cha...

Method of determining a memory state of a resistive memory cell and...

Integrated circuit with Resistivity changing memory cells and metho...

Memory circuit including a resistive memory element and method for...

Resistive memory arrangement

Memory circuit, method for operating a memory circuit, memory devic...

Resistive memory device and method for writing to a resistive memor...

Memory device and method for operating such a memory device

Semiconductor memory device

Method and memory circuit for operating a resistive memory cell

Charge-trapping memory device and methods for operating and manufac...

Methods for generating a reference voltage and for reading a memory...

Integrated memory device and method for operating the same

Integrated semiconductor memory with an arrangement of nonvolatile...

Multi-bit virtual-ground NAND memory device

Memory circuit and method for reading out a memory datum from such...

Semiconductor memory device comprising memory cells with floating g...

Resistive memory arrangement

Charge-trapping memory device including high permittivity strips

Patents Applicationslast 30 patents

Integrated Circuit and Method of Improved Determining a Memory Stat...

Method of Operating an Integrated Circuit, Integrated Circuit, and...

Integrated Circuit, Memory Module, Method of Operating an Integrate...

INTEGRATED CIRCUIT HAVING A MEMORY ARRAY

MEMORY CIRCUIT

Memory device and method of improving the reliability of a memory d...

Method of determining a memory state of a resistive memory cell and...

INTERGRATED CIRCUIT HAVING MEMORY WITH RESISTIVE MEMORY CELLS

METHOD AND MEMORY CIRCUIT FOR OPERATING A RESISTIVE MEMORY CELL

Memory circuit, method for operating a memory circuit, memory devic...

Resistive Memory Arrangement

Semiconductor memory device

Memory device and method for operating such a memory device

Methods for generating a reference voltage and for reading a memory...

Memory circuit having a resistive memory cell and method for operat...

CBRAM memory device and method for writing to a resistive memory ce...

Memory circuit including a resistive memory element and method for...

Memory circuit as well as method for evaluating a memory datum of a...

Memory comprising a memory device and a write unit configured as a...

Method for operating a PMC memory cell and CBRAM memory circuit

Multi-bit virtual-ground NAND memory device

Integrated semiconductor memory with an arrangement of nonvolatile...

Integrated memory device and method for operating the same

Memory circuit and method for reading out a memory datum from such...

Semiconductor memory with volatile and non-volatile memory cells

Charge-trapping memory device and methods for operating and manufac...

Resistive memory arrangement

Semiconductor memory device comprising memory cells with floating g...

Charge-trapping memory device and methods for operating and manufac...