Patent Application
20080273369
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
a shows a cross-sectional view of a solid electrolyte memory device set to a first memory state;
b shows a cross-sectional view of the solid electrolyte memory device of
According to one embodiment of the present invention, the resistivity changing memory cells are resistive memory cells.
According to one embodiment of the present invention, a memory device is provided which includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, a plurality of select devices, and a plurality of bit lines being connected to the memory cells. Each memory cell is arranged such that its current path input terminal is connected to a first bit line, and its current path output terminal is connected to a second bit line, wherein at least one memory cell and at least one select device are connected between the current path output terminal and the second bit line.
According to one embodiment of the present invention, the integrated circuit comprises a plurality of word lines being connected to the plurality of select devices.
According to one embodiment of the present invention, an integrated circuit having a memory device is provided which includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, a plurality of select devices, a plurality of bit lines being connected to the memory cells, and a plurality of word lines being connected to the plurality of select devices. Each memory cell is arranged such that its current path input terminal is connected to a first bit line, and its current path output terminal is connected to a second bit line, wherein at least one memory cell and at least one select device are connected between the current path output terminal and the second bit line.
According to one embodiment of the present invention, the current path output terminal of each memory cell is not grounded, but is connected to at least two current path output terminals of other memory cells. The current path which connects the current path output terminals of two different memory cells with each other runs through at least one select device. In order to connect two current path output terminals with each other, all select devices which are part of the current path connecting the two current path output terminals have to be activated, i.e., have to be switched into a conductive state. A current that is generated by a current generator flows, starting from the current generator, via a first bit line to the current path input terminal of the memory cell to be programmed, through the memory cell to be programmed, via corresponding select devices to the current path output terminals of other memory cells, through the other memory cells to respective current path input terminals of the other memory cells, and from the current path input terminals of the other memory cells via a second bit line back to the current generator. The current generated by the current generator may be a programming current used for programming the memory cell, or a current resulting from a programming voltage used for programming the memory cell.
Thus, the programming current flowing into the memory cell to be programmed can be split into different “returning currents” (i.e., each returning current flows via a memory cell, which is different from the memory cell to be programmed, back to the programming current generator). As a consequence, the corresponding select devices have to deal only with a part of the programming current. As a consequence, the dimensions of the select devices can be reduced which means that the shrinking potential of the memory device is increased. In other words, in order to program a memory cell, several select devices are used (the select devices are shared between the memory cells). In this way, it is possible to use several select devices to route the programming current back to the programming current generator which means that the requirements concerning the maximum strength of a current which can be routed through the select device can be reduced.
According to one embodiment of the present invention, the current output terminal of each programmable memory cell is connected to the second bit line via a first current path and a second current path connected in parallel, wherein the first current path runs through a first select device and a first memory cell, and wherein the second current path runs through a second select device and a second memory cell.
According to one embodiment of the present invention, the first memory cell and the second memory cell are neighboring memory cells of the programmable memory cell.
According to one embodiment of the present invention, the first select device and the second select device are directly connected to the programmable memory cell.
According to one embodiment of the present invention, the select devices are arranged as a select device matrix including select device columns and select device rows.
According to one embodiment of the invention, all select devices of a select device row are connected in series with each other.
According to one embodiment of the present invention, all select devices of a select device column are connected to the same word line.
According to one embodiment of the present invention, all select devices of a select device row are connected to different word lines.
According to one embodiment of the present invention, the first bit line and the second bit line, which are assigned to a memory cell, are neighboring bit lines, respectively. However, the invention is not restricted thereto. Between the first bit line and the second bit line, which are assigned to a memory cell, at least one further bit line may be arranged.
According to one embodiment of the present invention, the first bit line and the second bit line, which are assigned to a memory cell, are usable for programming the memory cell and for determining the memory state of the memory cell.
According to one embodiment of the present invention, an integrated circuit having a memory device is provided, the memory device including a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, and a plurality of select devices. Each current path output terminal is connected to at least one different current path output terminal via at least one select device.
According to one embodiment of the present invention, a memory device is provided, the memory device including a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, and a plurality of select devices. Each current path output terminal is connected to at least one different current path output terminal via at least one select device.
According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory means including a current path input means and a current path output means, respectively, and a plurality of select means, wherein each current path output means is connected to at least one different current path output means via at least one select means.
According to one embodiment of the present invention, the resistivity changing memory means is a resistivity changing memory cell, for example a MRAM cell, a CBRAM cell, or a PCRAM cell, the current path input means is a current path input terminal, the current path output means is a current path output terminal, and the select means is a select device, for example a select transistor.
According to one embodiment of the present invention, a memory module having at least one integrated circuit or memory device according to one embodiment of the present invention is provided. According to one embodiment of the present invention, the memory module is stackable.
According to one embodiment of the present invention, a method of operating a memory cell of an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, a plurality of select devices, and a plurality of bit lines being connected to the memory cells. Each memory cell is arranged such that its current path input terminal is connected to a first bit line, and its current path output terminal is connected to a second bit line, wherein at least one memory cell and at least one select device are connected between the current path output terminal and the second bit line. The method includes activating at least two current paths between the current path output terminal of the memory cell and the second bit line assigned to the memory cell by activating all select devices being part of that current path, and routing a programming current from the first bit line through the memory cell to the second bit line via the at least two activated current paths. Alternatively or additionally, at least one current path is activated between the current output terminal of the memory cell and the second bit line assigned to the memory cell by activating all select devices being part of that current path, and a sensing current is routed from the first bit line through the memory cell to the second bit line via the at least one activated current path.
According to one embodiment of the present invention, the integrated circuit includes a plurality of word lines being connected to the select devices.
According to one embodiment of the present invention, a method of operating a memory cell of a memory device is provided. The memory device includes a plurality of resistivity changing memory cells including a current path input terminal and a current path output terminal, respectively, a plurality of select devices, and a plurality of bit lines being connected to the memory cells. Each memory cell is arranged such that its current path input terminal is connected to a first bit line, and its current path output terminal is connected to a second bit line, wherein at least one memory cell and at least one select device are connected between the current path output terminal and the second bit line. The method includes activating at least two current paths between the current path output terminal of the memory cell and the second bit line assigned to the memory cell by activating all select devices being part of that current path, and routing a programming current from the first bit line through the memory cell to the second bit line via the at least two activated current paths. Alternatively or additionally, at least one current path is activated between the current output terminal of the memory cell and the second bit line assigned to the memory cell by activating all select devices being part of that current path, and a sensing current is routed from the first bit line through the memory cell to the second bit line via the at least one activated current path.
According to one embodiment of the present invention, the integrated circuit includes a plurality of word lines being connected to the select devices.
The present invention further provides a computer program product being configured to perform, when being executed on a computing device, the method of operating a memory cell according to one embodiment of the present invention. Further, the present invention provides a data carrier configured to store a computer program product according to the present invention.
All embodiments of memory devices which have been discussed above can be applied to the embodiments of the operating method according to the present invention.
According to one embodiment of the present invention, the memory cells of the memory device are designed such that they can be programmed using programming currents (i.e., currents are used for forming and erasing conductive paths within the memory cells). According to one embodiment of the present invention, the strengths of the programming currents may range up to 500 μA. According to one embodiment of the present invention, the strengths of the programming currents may range up to 1 mA.
According to one embodiment of the present invention, the memory cells are programmable metallization memory cells, e.g., solid electrolyte memory cells (e.g., conductive bridging random access memory (CBRAM) cells), magneto resistive memory cells (e.g., magneto resistive random access memory (MRAM) cells), phase changing memory cells (e.g., phase changing random access memory (PCRAM) cells), or organic memory cells (e.g., organic random access memory (ORAM) cells). However, the present invention is not restricted thereto. Any type of memory cell which can be programmed with programming currents (or programming voltages) falls under the scope of the present invention.
The type of the select devices may be freely chosen. For example, the selecting devices are transistors.
Since the embodiments of the present invention can be applied to programmable metallization cell (PMC) devices (e.g., solid electrolyte devices like conductive bridging random access memory (CBRAM) devices), in the following description, making reference to
As shown in
In the context of this description, chalcogenide material (ion conductor) is to be understood for example as any compound containing oxygen, sulphur, selenium, germanium and/or tellurium. In accordance with one embodiment of the invention, the ion conducting material is for example a compound, which is made of a chalcogenide and at least one metal from group I or group II of the periodic system, for example arsenic-trisulfide-silver. Alternatively, the chalcogenide material contains germanium-sulfide (GeSx), germanium-selenide (GeSex), tungsten oxide (WOx), copper sulfide (CuSx), or the like. The ion conducting material may be a solid state electrolyte. Furthermore, the ion conducting material can be made of a chalcogenide material containing metal ions, wherein the metal ions can be made of a metal, which is selected from a group consisting of silver, copper and zinc or of a combination or an alloy of these metals.
If a voltage as indicated in
One way to determine the current memory status of a CBRAM cell is to route a sensing current through the CBRAM cell, as an example. The sensing current experiences a high resistance when no conductive bridge 107 exists within the CBRAM cell and experiences a low resistance when a conductive bridge 107 exists within the CBRAM cell. A high resistance may for example represent “0”, whereas a low resistance represents “1”, or vice versa. The memory status detection may also be carried out using sensing voltages.
Each memory cell 201 is arranged such that its current path input terminal 202 is connected to one of a plurality of bit lines 2051 to 2056, and its current path output terminal 203 is connected to another one of the plurality of bit lines 2051 to 2056. At least one memory cell 201 and at least one select device 204 are connected between the current path output terminal 203 of a memory cell 201 and the second bit line 205 to which the current path output terminal 203 is connected. For example, a memory cell 207 to be programmed includes a current path input terminal 208 and a current path output terminal 209, wherein the current path input terminal 208 is connected to a first bit line 2052, and the current path output terminal 209 is connected to a second bit line 2051. The current path input terminal 208 is directly connected to the first bit line 2052, whereas the current path output terminal 209 is connected to the second bit line 2051 via a first current path and a second current path. The first current path runs through a first select device 212 and a first memory cell 213. The second current path runs through a second select device 214 and a second memory cell 215. The first memory cell 213 and the second memory cell 215 are neighboring memory cells of the memory cell 207 to be programmed. The first bit line 2052 and the second bit line 2051 are neighboring bit lines.
The memory cells 201 are arranged as memory cell matrix including memory cell rows 216 and memory cell columns 217. In the same way, the select devices 204 form a select device matrix including select device rows 218 and select device columns 219. All select devices 204 of one select device row 218 are connected in series. Further, each select device 204 is directly connected to the current path output terminals 209 of two neighboring memory cells 201 of one memory cell row 216. The current path input terminals 202 of the memory cells 201 belonging to the same memory cell row 216 are alternately connected to two different neighboring bit lines 205. All select devices 204 of one select device column 219 are controlled by the same word line 206. All select devices 204 of a select device row 218 are connected to different word lines 206, i.e., each select device 204 of a select device row 218 is controlled by an “own” word line 206.
The second select device 214 may be activated in a way that the current strengths of the current flowing through the second memory cell 215 do not exceed a predetermined current strength threshold value. In this way, it is ensured that the sensing current flowing through the second memory cell 215 does not change the memory state of the second memory cell 215.
Also in this embodiment it may be possible to control the first select device 212 and the second select device 214 such that the currents flowing through the first memory cell 213 and the second memory cell 215 do not change the memory states of these memory cells. Thus, the first select device 212 and the second select device 214 are used as current limiters.
The memory device 500 includes a plurality of stripe shaped bit lines 205 being arranged parallel to each other, and a plurality of word lines 206 being arranged parallel to each other. The bit lines 205 are arranged perpendicular to the word lines 206. The bit lines 205 contact memory cells 201, wherein two neighboring bit lines 205 contact every second memory cell 201 of the same memory cell row 216. In other words, each bit line 205 is connected to the current path input terminals of two memory cells 201 within an area 501 extending between four neighboring word lines 206.
The architecture of the memory device 600 is similar to the architecture of the memory device 500 shown in
As shown in
As shown in
As shown in
In accordance with some embodiments of the invention, memory devices/integrated circuits as described herein may be used in a variety of applications or systems, such as the illustrative computing system shown in
The wireless communication apparatus 1110 may have the ability to send and/or receive transmissions over a cellular telephone network, a WiFi wireless network, or other wireless communication network. It will be understood that the various input/output devices shown in
According to one embodiment of the invention, the resistivity changing memory cells are phase changing memory cells that include a phase changing material. The phase changing material can be switched between at least two different crystallization states (i.e., the phase changing material may adopt at least two different degrees of crystallization), wherein each crystallization state may be used to represent a memory state. When the number of possible crystallization states is two, the crystallization state having a high degree of crystallization is also referred to as a “crystalline state”, whereas the crystallization state having a low degree of crystallization is also referred to as an “amorphous state”. Different crystallization states can be distinguished from each other by their differing electrical properties, and in particular by their different resistances. For example, a crystallization state having a high degree of crystallization (ordered atomic structure) generally has a lower resistance than a crystallization state having a low degree of crystallization (disordered atomic structure). For sake of simplicity, it will be assumed in the following description that the phase changing material can adopt two crystallization states (an “amorphous state” and a “crystalline state”), however it will be understood that additional intermediate states may also be used.
Phase changing memory cells may change from the amorphous state to the crystalline state (and vice versa) due to temperature changes of the phase changing material. These temperature changes may be caused using different approaches. For example, a current may be driven through the phase changing material (or a voltage may be applied across the phase changing material). Alternatively, a current or a voltage may be fed to a resistive heater which is disposed adjacent to the phase changing material. To determine the memory state of a resistivity changing memory cell, a sensing current may be routed through the phase changing material (or a sensing voltage may be applied across the phase changing material), thereby sensing the resistivity of the resistivity changing memory cell, which represents the memory state of the memory cell.
The phase changing material 1204 may include a variety of materials. According to one embodiment, the phase changing material 1204 may include or consist of a chalcogenide alloy that includes one or more elements from group VI of the periodic table. According to another embodiment, the phase changing material 1204 may include or consist of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe or AgInSbTe. According to a further embodiment, the phase changing material 1204 may include or consist of chalcogen free material, such as GeSb, GaSb, InSb, or GeGaInSb. According to still another embodiment, the phase changing material 1204 may include or consist of any suitable material including one or more of the elements Ge, Sb, Te, Ga, Bi, Pb, Sn, Si, P, O, As, In, Se, and S.
According to one embodiment, at least one of the first electrode 1202 and the second electrode 1206 may include or consist of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, or mixtures or alloys thereof. According to another embodiment, at least one of the first electrode 1202 and the second electrode 1206 may include or consist of Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W and two or more elements selected from the group consisting of B, C, N, O, Al, Si, P, S, and/or mixtures and alloys thereof. Examples of such materials include TiCN, TiAlN, TiSiN, W—Al2O3 and Cr—Al2O3.
As already indicated, the phase changing material of the phase changing memory cells 1306a, 1306b, 1306c, 1306d may be changed from the amorphous state to the crystalline state (or vice versa) under the influence of a temperature change. More generally, the phase changing material may be changed from a first degree of crystallization to a second degree of crystallization (or vice versa) under the influence of a temperature change. For example, a bit value “0” may be assigned to the first (low) degree of crystallization, and a bit value “1” may be assigned to the second (high) degree of crystallization. Since different degrees of crystallization imply different electrical resistances, the sense amplifier 1308 is capable of determining the memory state of one of the phase changing memory cells 1306a, 1306b, 1306c, or 1306d depending on the resistance of the phase changing material.
To achieve high memory densities, the phase changing memory cells 1306a, 1306b, 1306c, 1306d may be capable of storing multiple bits of data, i.e., the phase changing material may be programmed to more than two resistance values. For example, if a phase changing memory cell 1306a, 1306b, 1306c, 1306d is programmed to one of three possible resistance levels, 1.5 bits of data per memory cell can be stored. If the phase changing memory cell is programmed to one of four possible resistance levels, two bits of data per memory cell can be stored, and so on.
The embodiment shown in
Another type of resistivity changing memory cell may be formed using carbon as a resistivity changing material. Generally, amorphous carbon that is rich is sp3-hybridized carbon (i.e., tetrahedrally bonded carbon) has a high resistivity, while amorphous carbon that is rich in sp2-hybridized carbon (i.e., trigonally bonded carbon) has a low resistivity. This difference in resistivity can be used in a resistivity changing memory cell.
In one embodiment, a carbon memory cell may be formed in a manner similar to that described above with reference to phase changing memory cells. A temperature-induced change between an sp3-rich state and an sp2-rich state may be used to change the resistivity of an amorphous carbon material. These differing resistivities may be used to represent different memory states. For example, a high resistance sp3-rich state can be used to represent a “0”, and a low resistance sp2-rich state can be used to represent a “1”. It will be understood that intermediate resistance states may be used to represent multiple bits, as discussed above.
Generally, in this type of carbon memory cell, application of a first temperature causes a change of high resistivity sp3-rich amorphous carbon to relatively low resistivity sp2-rich amorphous carbon. This conversion can be reversed by application of a second temperature, which is typically higher than the first temperature. As discussed above, these temperatures may be provided, for example, by applying a current and/or voltage pulse to the carbon material. Alternatively, the temperatures can be provided by using a resistive heater that is disposed adjacent to the carbon material.
Another way in which resistivity changes in amorphous carbon can be used to store information is by field-strength induced growth of a conductive path in an insulating amorphous carbon film. For example, applying voltage or current pulses may cause the formation of a conductive sp2 filament in insulating sp3-rich amorphous carbon. The operation of this type of resistive carbon memory is illustrated in
Resistivity changing memory cells, such as the phase changing memory cells and carbon memory cells described above, may include a transistor, a diode, or another active component for selecting the memory cell.
To write to the memory cell 1500, the word line 1514 is used to select the memory cell 1500, and a current (or voltage) pulse on the bit line 1508 is applied to the resistivity changing memory element 1504, changing the resistance of the resistivity changing memory element 1504. Similarly, when reading the memory cell 1500, the word line 1514 is used to select the memory cell 1500, and the bit line 1508 is used to apply a reading voltage (or current) across the resistivity changing memory element 1504 to measure the resistance of the resistivity changing memory element 1504.
The memory cell 1500 may be referred to as a 1T1J cell, because it uses one transistor and one memory junction (the resistivity changing memory element 1504). Typically, a memory device will include an array of many such cells. It will be understood that other configurations for a 1T1J memory cell, or configurations other than a 1T1J configuration, may be used with a resistivity changing memory element. For example, in
In the following description, further aspects of the present invention will be explained.
According to one embodiment of the present invention, large cell areas are avoided. Further, the supply voltages of the memory chip are decreased.
Future MRAM (magneto-resistive random access memory) write concepts may require a large write current to be driven through an access transistor. According to one embodiment of the present invention, the write currents through the array access transistor may range up to 500 μA, even up to 1 mA (MRAM). Also future PCRAM (phase changing random access memory) write concepts may require high write currents. According to one embodiment of the present invention, the write currents through the array access transistor may range up to 300 μA-400 μA (PCRAM). The result is that the array access transistor has to show a low resistance and a large width. A large array transistor width causes a die area penalty. Further, the cell size is very large with a usual FET. In addition, the ON-resistance of the array access transistor causes a large voltage drop over the array access transistor. As a consequence, the supply voltage of the memory chip will increase. This causes many challenges to the periphery circuits (charge pumps, etc.). The same problems can be found in many types of non-volatile resistive memories.
One cell unit contains three select devices. The sharing of the select device terminals which are connected to a resistive memory cell enables the reduction of the die area in the array. The select transistor may for example be a field effect transistor, a finFET transistor or a bipolar transistor.
Different variations in the layout are possible:
If large currents are driven through the select device, and the metal levels are limited, a 10 F2 per bit cell is possible. In the embodiment shown in
If the cells are arranged in a stacked manner, a 4 F2 per bit cell is possible. The width of the select device is reduced to one F due to the different metal levels of the bit lines. The cell size in the word line direction is equal to the 10 F per bit cell (4 F). If the memory cells are also stacked, different memory cells with different resistances can be processed. This may for example be possible in MRAM cells due to different magnetic tunnel junction thicknesses.
According to one embodiment of the present invention, during a read cycle, the word line, which neighboured cell should be read out, opens the select device. All other select devices are closed. Between the bit lines of the selected resistive cells a voltage potential difference is applied. This potential difference generates a cell resistance dependent current on the bit lines. This current can be sensed.
According to one embodiment of the present invention, during a write cycle, two write concepts may be adopted: 1.) a heat current may be routed through the cell followed by a field current on the bit line (like thermal select); and 2.) only one current may be routed through the cell (like spin torque or thermal assisted spin torque).
According to one embodiment of the present invention, if a current has to be routed through a selected cell, the two word lines being closest to the selected cell open the two select devices which are connected to the selected cell. The write current is applied on a bit line, and the write current flows back over the stacked bit line. The benefit is that the two select transistors that are connected in series with a cell are connected parallel on the next bit line. So the effective resistance of the select device is halved.
As used herein, the terms “connected” and “coupled” are intended to include both direct and indirect connection and coupling, respectively.
The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the disclosed teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined solely by the claims appended hereto.
